Source Code for Module envi.archs.z80.disasm

  1   
  2  import envi 
  3  import envi.bits as e_bits 
  4  import envi.bytesig as e_bsig 
  5   
  6  from envi.archs.z80.regs import * 
  7  from envi.archs.z80.const import * 
  8   
  9  import envi.archs.z80.z80opcode as z80_opcode 
 10   
 11  sigtree = e_bsig.SignatureTree() 
 12   
 13  for row in z80_opcode.z80table: 
 14      sighex, maskhex = row[0] 
 15   
 16      sig = sighex.decode('hex') 
 17      mask = maskhex.decode('hex') 
 18   
 19      sigtree.addSignature(sig, masks=mask, val=row) 
 20   
 21   
 22 -class z80RegOper(envi.RegisterOper): 
 23 -    def __init__(self, reg): 
 24          self.reg = reg 
 25   
 26 -class z80ImmOper(envi.ImmedOper): 
 27 -    def __init__(self, imm): 
 28          self.imm = imm 
 29   
 30 -    def repr(self, op): 
 31          return '%.4xH' % self.imm 
 32   
 33 -class z80ConstOper(z80ImmOper): 
 34      pass 
 35   
 36 -class z80RegMem(envi.DerefOper): 
 37 -    def __init__(self, reg, disp = 0): 
 38          self.reg = reg 
 39          self.disp = disp 
 40   
 41 -    def repr(self, op): 
 42          rname = regctx.getRegisterName(self.reg) 
 43          if self.disp > 0: 
 44              return '(%s + %d)' % (rname, self.disp) 
 45          if self.disp < 0: 
 46              return '(%s - %d)' % (rname, abs(self.disp)) 
 47          return '(%s)' % rname 
 48   
 49 -class z80Opcode(envi.Opcode): 
 50      pass 
 51   
 52 -class z80Disasm: 
 53   
 54 -    def __init__(self): 
 55          # NOTE: For eventual things like "modes" etc... 
 56          pass 
 57   
 58 -    def disasm(self, bytes, offset, va): 
 59          row = sigtree.getSignature(bytes, offset) 
 60          if row == None: 
 61              raise envi.InvalidInstruction(bytes=bytes[offset:offset+8]) 
 62          sigmask, mnem, o1type, o1info, o2type, o2info, oplen, immoff, iflags = row 
 63          #ret = i386Opcode(va, optype, mnem, prefixes, (offset-startoff)+operoffset, operands, iflags) 
 64          opers = [] 
 65          if o1type != None: 
 66              opers.append(self._buildOper(bytes, offset, immoff, o1type, o1info)) 
 67          if o2type != None: 
 68              opers.append(self._buildOper(bytes, offset, immoff, o2type, o2info)) 
 69          return z80Opcode(va, 0, mnem, 0, oplen, opers, iflags) 
 70   
 71 -    def _buildOper(self, bytes, offset, immoff, otype, oinfo): 
 72   
 73          if otype == OPTYPE_Reg: 
 74              return z80RegOper(oinfo) 
 75   
 76          elif otype == OPTYPE_RegMem: 
 77              return z80RegMem(oinfo) 
 78   
 79          elif otype == OPTYPE_const: 
 80              return z80ConstOper(oinfo) 
 81   
 82          elif otype == OPTYPE_imm8: 
 83              imm = e_bits.parsebytes(bytes, offset+immoff, 1) 
 84              return z80ImmOper(imm) 
 85   
 86          elif otype == OPTYPE_imm16: 
 87              imm = e_bits.parsebytes(bytes, offset+immoff, 2) 
 88              return z80ImmOper(imm) 
 89   
 90          elif otype == OPTYPE_RegAlt: 
 91              print 'REG ALT!' 
 92              return z80RegOper(oinfo) 
 93   
 94          elif otype == OPTYPE_Ind: 
 95              print 'OPTYPE IND' 
 96   
 97          elif otype == OPTYPE_RegMemDisp: 
 98              disp = e_bits.parsebytes(bytes, offset+immoff, 1, sign=True) 
 99              return z80RegMem(oinfo, disp) 
100   
101          else: 
102              raise Exception('Unknown z80 operand type: %d' % otype) 
103   
104  if __name__ == '__main__': 
105      print sigtree.getSignature('\x00') 
106      print sigtree.getSignature('fdcb0006'.decode('hex')) 
107   
108      d = z80Disasm() 
109   
110      print repr(d.disasm('\xfd\xcb\x30\x06', 0, 20)) 
111