Source Code for Module envi.archs.i386.regs

 1  """
 
 2  Home of the i386 module's register specs/code.
 
 3  """ 
 4  import envi.registers as e_reg 
 5  
 
 6  ## Definitions for some of the i386 MSRs from intel...
 
 7  MSR_DEBUGCTL             = 0x01d9 # Intel p4 and forward, debug behavior control 
 8  MSR_DEBUGCTL_LBR         = 0x0001 # last branch recording (in msr's) 
 9  MSR_DEBUGCTL_BTF         = 0x0002 # single-step on branches (break on branch) 
10  MSR_DEBUGCTL_TR          = 0x0004 # enable sending "branch trace messages" !! 
11  MSR_DEBUGCTL_BTS         = 0x0008 # enable logging BTMs to circular buffer 
12  MSR_DEBUGCTL_BTINT       = 0x0010 # Branch-trace-interrupt (gen interrupt on BTS full) 
13  MSR_DEBUGCTL_BTS_OFF_OS  = 0x0020 # disable ring0 branch trace store 
14  MSR_DEBUGCTL_BTS_OFF_USR = 0x0040 # disable non-ring0 branch trace store 
15  
 
16  MSR_SYSENTER_EIP         = 0x0176 # Where is EIP at sysenter? 
17  
 
18  IA32_DS_AREA_MSR         = 0x0600 # pointer to the configured debug storage area 
19  
 
20  # Eflags bit masks
 
21  EFLAGS_CF = 1 << 0 
22  EFLAGS_PF = 1 << 2 
23  EFLAGS_AF = 1 << 4 
24  EFLAGS_ZF = 1 << 6 
25  EFLAGS_SF = 1 << 7 
26  EFLAGS_TF = 1 << 8 
27  EFLAGS_IF = 1 << 9 
28  EFLAGS_DF = 1 << 10 
29  EFLAGS_OF = 1 << 11 
30  
 
31  i386regs = [
 
32      ("eax",32),("ecx",32),("edx",32),("ebx",32),("esp",32),("ebp",32),("esi",32),("edi",32),
 
33      #FIXME are these 64?
 
34      ("mm0",64),("mm1",64), ("mm2",64), ("mm3",64), ("mm4",64), ("mm5",64), ("mm6",64), ("mm7",64),
 
35      # SIMD registers
 
36      ("xmm0",128),("xmm1",128),("xmm2",128),("xmm3",128),("xmm4",128),("xmm5",128),("xmm6",128),("xmm7",128),
 
37      # Debug registers
 
38      ("debug0",32),("debug1",32),("debug2",32),("debug3",32),("debug4",32),("debug5",32),("debug6",32),("debug7",32),
 
39      # Control registers
 
40      ("ctrl0",32),("ctrl1",32),("ctrl2",32),("ctrl3",32),("ctrl4",32),("ctrl5",32),("ctrl6",32),("ctrl7",32),
 
41      # Test registers
 
42      ("test0", 32),("test1", 32),("test2", 32),("test3", 32),("test4", 32),("test5", 32),("test6", 32),("test7", 32),
 
43      # Segment registers
 
44      ("es", 16),("cs",16),("ss",16),("ds",16),("fs",16),("gs",16),
 
45      # FPU Registers
 
46      ("st0", 128),("st1", 128),("st2", 128),("st3", 128),("st4", 128),("st5", 128),("st6", 128),("st7", 128),
 
47      # Leftovers ;)
 
48      ("eflags", 32), ("eip", 32),
 
49  ] 
50  
 
51 -def getRegOffset(regs, regname): 
52      # NOTE: dynamically calculate this on import so we are less
 
53      # likely to fuck it up...
 
54      for i,(name,width) in enumerate(regs): 
55          if name == regname: 
56              return i 
57      raise Exception("getRegOffset doesn't know about: %s" % regname) 
58  
 
59  # Setup REG_EAX and the like in our module
 
60  l = locals() 
61  e_reg.addLocalEnums(l, i386regs) 
62  
 
63  i386meta = [
 
64      ("ax", REG_EAX, 0, 16),
 
65      ("cx", REG_ECX, 0, 16),
 
66      ("dx", REG_EDX, 0, 16),
 
67      ("bx", REG_EBX, 0, 16),
 
68      ("sp", REG_ESP, 0, 16),
 
69      ("bp", REG_EBP, 0, 16),
 
70      ("si", REG_ESI, 0, 16),
 
71      ("di", REG_EDI, 0, 16),
 
72  
 
73      ("al", REG_EAX, 0, 8),
 
74      ("cl", REG_ECX, 0, 8),
 
75      ("dl", REG_EDX, 0, 8),
 
76      ("bl", REG_EBX, 0, 8),
 
77  
 
78      ("ah", REG_EAX, 8, 8),
 
79      ("ch", REG_ECX, 8, 8),
 
80      ("dh", REG_EDX, 8, 8),
 
81      ("bh", REG_EBX, 8, 8),
 
82  
 
83      # FIXME more flags... (here and amd64)
 
84      ("TF", REG_EFLAGS, 8, 1),
 
85  ] 
86  
 
87  e_reg.addLocalMetas(l, i386meta) 
88  
 
89  
 
90 -class i386RegisterContext(e_reg.RegisterContext): 
91 -    def __init__(self): 
92          e_reg.RegisterContext.__init__(self) 
93          self.loadRegDef(i386regs) 
94          self.loadRegMetas(i386meta) 
95          self.setRegisterIndexes(REG_EIP, REG_ESP) 
96