Package envi :: Package archs :: Package i386 :: Module opcode86

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Module opcode86

source code

Variables

[hide private]

INSTR_PREFIX = 4026531840

PREFIX_LOCK = 1048576

PREFIX_REPNZ = 2097152

PREFIX_REPZ = 4194304

PREFIX_REP = 8388608

PREFIX_REP_SIMD = 16777216

PREFIX_OP_SIZE = 33554432

PREFIX_ADDR_SIZE = 67108864

PREFIX_SIMD = 134217728

PREFIX_CS = 268435456

PREFIX_SS = 536870912

PREFIX_DS = 805306368

PREFIX_ES = 1073741824

PREFIX_FS = 1342177280

PREFIX_GS = 1610612736

PREFIX_REG_MASK = 4026531840

ADDRMETH_A = 65536

ADDRMETH_C = 131072

ADDRMETH_D = 196608

ADDRMETH_E = 262144

ADDRMETH_F = 327680

ADDRMETH_G = 393216

ADDRMETH_I = 458752

ADDRMETH_J = 524288

ADDRMETH_M = 589824

ADDRMETH_N = 655360

ADDRMETH_O = 720896

ADDRMETH_P = 786432

ADDRMETH_Q = 851968

ADDRMETH_R = 917504

ADDRMETH_S = 983040

ADDRMETH_U = 1048576

ADDRMETH_V = 1114112

ADDRMETH_W = 1179648

ADDRMETH_X = 1245184

ADDRMETH_Y = 1310720

OPTYPE_a = 16777216

OPTYPE_b = 33554432

OPTYPE_c = 50331648

OPTYPE_d = 67108864

OPTYPE_dq = 83886080

OPTYPE_p = 100663296

OPTYPE_pi = 117440512

OPTYPE_ps = 134217728

OPTYPE_pd = 134217728

OPTYPE_q = 150994944

OPTYPE_s = 167772160

OPTYPE_ss = 184549376

OPTYPE_si = 201326592

OPTYPE_sd = 201326592

OPTYPE_v = 218103808

OPTYPE_w = 234881024

OPTYPE_z = 251658240

OPTYPE_fs = 268435456

OPTYPE_fd = 536870912

OPTYPE_fe = 805306368

OPTYPE_fb = 1073741824

OPTYPE_fv = 1342177280

OPERSIZE = {0: (2, 4, 8), 16777216: (2, 4, 4), 33554432: (1, 1...

INS_EXEC = 4096

INS_ARITH = 8192

INS_LOGIC = 12288

INS_STACK = 16384

INS_COND = 20480

INS_LOAD = 24576

INS_ARRAY = 28672

INS_BIT = 32768

INS_FLAG = 36864

INS_FPU = 40960

INS_TRAPS = 53248

INS_SYSTEM = 57344

INS_OTHER = 61440

INS_BRANCH = 4097

INS_BRANCHCC = 4098

INS_CALL = 4099

INS_CALLCC = 4100

INS_RET = 4101

INS_LOOP = 4102

INS_ADD = 8193

INS_SUB = 8194

INS_MUL = 8195

INS_DIV = 8196

INS_INC = 8197

INS_DEC = 8198

INS_SHL = 8199

INS_SHR = 8200

INS_ROL = 8201

INS_ROR = 8202

INS_AND = 12289

INS_OR = 12290

INS_XOR = 12291

INS_NOT = 12292

INS_NEG = 12293

INS_PUSH = 16385

INS_POP = 16386

INS_PUSHREGS = 16387

INS_POPREGS = 16388

INS_PUSHFLAGS = 16389

INS_POPFLAGS = 16390

INS_ENTER = 16391

INS_LEAVE = 16392

INS_TEST = 20481

INS_CMP = 20482

INS_MOV = 24577

INS_MOVCC = 24578

INS_XCHG = 24579

INS_XCHGCC = 24580

INS_LEA = 24581

INS_STRCMP = 28673

INS_STRLOAD = 28674

INS_STRMOV = 28675

INS_STRSTOR = 28676

INS_XLAT = 28677

INS_BITTEST = 32769

INS_BITSET = 32770

INS_BITCLR = 32771

INS_CLEARCF = 36865

INS_CLEARZF = 36866

INS_CLEAROF = 36867

INS_CLEARDF = 36868

INS_CLEARSF = 36869

INS_CLEARPF = 36870

INS_SETCF = 36871

INS_SETZF = 36872

INS_SETOF = 36873

INS_SETDF = 36874

INS_SETSF = 36875

INS_SETPF = 36876

INS_TOGCF = 36880

INS_TOGZF = 36896

INS_TOGOF = 36912

INS_TOGDF = 36928

INS_TOGSF = 36944

INS_TOGPF = 36960

INS_TRAP = 53249

INS_TRAPCC = 53250

INS_TRET = 53251

INS_BOUNDS = 53252

INS_DEBUG = 53253

INS_TRACE = 53254

INS_INVALIDOP = 53255

INS_OFLOW = 53256

INS_HALT = 57345

INS_IN = 57346

INS_OUT = 57347

INS_CPUID = 57348

INS_NOP = 61441

INS_BCDCONV = 61442

INS_SZCONV = 61443

OP_R = 1

OP_W = 2

OP_X = 4

OP_UNK = 0

OP_REG = 256

OP_IMM = 512

OP_REL = 768

OP_ADDR = 1024

OP_EXPR = 1280

OP_PTR = 1536

OP_OFF = 1792

OP_SIGNED = 4096

OP_STRING = 8192

OP_CONST = 16384

OP_EXTRASEG = 65536

OP_CODESEG = 131072

OP_STACKSEG = 196608

OP_DATASEG = 262144

OP_DATA1SEG = 327680

OP_DATA2SEG = 393216

ARG_NONE = 0

cpu_8086 = 4096

cpu_80286 = 8192

cpu_80386 = 12288

cpu_80387 = 16384

cpu_80486 = 20480

cpu_PENTIUM = 24576

cpu_PENTPRO = 28672

cpu_PENTMMX = 32768

cpu_PENTIUM2 = 36864

cpu_AMD64 = 40960

x86_MAIN = 0

x86_0F = 1

x86_80 = 2

tbl32_Main = [(0, 8193, 33816578, 33947649, 0, 12288, 'add', 0...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_0F = [(16, 0, 0, 0, 0, 12288, 0, 0, 0, 0), (17, 0, 0, 0,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_660F = [(16, 0, 0, 0, 0, 12288, 0, 0, 0, 0), (17, 0, 0, ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_F20F = [(16, 0, 0, 0, 0, 12288, 0, 0, 0, 0), (17, 0, 0, ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_F30F = [(16, 0, 0, 0, 0, 12288, 0, 0, 0, 0), (17, 0, 0, ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_0F00 = [(0, 57344, 235143169, 0, 0, 12288, 'sldt', 0, 0,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_0F01_00BF = [(0, 57344, 168361985, 0, 0, 12288, 'sgdt', ...

tbl32_0F01_rest = [(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), (0, 57344, ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_0F18 = [(0, 57344, 589826, 0, 0, 36864, 'prefetch', 0, 0...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_0F71 = [(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), (0, 0, 0, 0, 0, ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_0F72 = [(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), (0, 0, 0, 0, 0, ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_0F73 = [(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), (0, 0, 0, 0, 0, ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_660F73 = [(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), (0, 0, 0, 0, 0...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_0FAE_00BF = [(0, 40960, 218365954, 0, 0, 32768, 'fxsave'...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_0FAE_rest = [(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), (0, 0, 0, 0...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_0FBA = [(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), (0, 0, 0, 0, 0, ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_0FC2 = [(0, 24580, 151584770, 0, 0, 24576, 'cmpxch8b', 0...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_0FC7_00BF = [(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), (0, 24580, ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_0FC7_rest = [(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), (0, 0, 0, 0...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_660FC7_00BF = [(0, 24580, 151584770, 0, 0, 24576, 'cmpxc...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_660FC7_rest = [(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), (0, 0, 0,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_F20FC7_00BF = [(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), (0, 0, 0,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_F20FC7_rest = [(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), (0, 0, 0,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_F30FC7_00BF = [(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), (0, 0, 0,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_F30FC7_rest = [(0, 0, 0, 0, 0, 0, 0, 0, 0, 0), (0, 0, 0,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_80 = [(0, 8193, 33816578, 34017281, 0, 12288, 'add', 0, ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_81 = [(0, 8193, 218365954, 252121089, 0, 12288, 'add', 0...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_82 = [(0, 8193, 33816578, 34017281, 0, 12288, 'add', 0, ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_83 = [(0, 8193, 218365954, 34017281, 0, 12288, 'add', 0,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_C0 = [(0, 8201, 33816578, 34013185, 0, 12288, 'rol', 0, ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_C1 = [(0, 8201, 218365954, 34013185, 0, 12288, 'rol', 0,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_D0 = [(0, 8201, 33816578, 513, 0, 12288, 'rol', 0, 1, 0)...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_D1 = [(0, 8201, 218365954, 513, 0, 12288, 'rol', 0, 1, 0...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_D2 = [(0, 8201, 33816578, 257, 0, 12288, 'rol', 0, 52428...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_D3 = [(0, 8201, 218365954, 257, 0, 12288, 'rol', 0, 5242...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_F6 = [(0, 20481, 33816577, 34017281, 0, 12288, 'test', 0...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_F7 = [(0, 20481, 218365953, 252116993, 0, 12288, 'test',...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_FE = [(0, 8197, 33816578, 0, 0, 12288, 'inc', 0, 0, 0), ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_FF = [(0, 8197, 218365954, 0, 0, 12288, 'inc', 0, 0, 0),...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_fpuD8_00BF = [(0, 40960, 269025282, 0, 0, 16384, 'fadd',...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_fpuD8_rest = [(0, 40960, 258, 257, 0, 16384, 'fadd', 54,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_fpuD9_00BF = [(0, 40960, 269025282, 0, 0, 16384, 'fld', ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_fpuD9_rest = [(0, 40960, 258, 257, 0, 16384, 'fld', 54, ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_fpuDA_00BF = [(0, 40960, 67698690, 0, 0, 16384, 'fiadd',...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_fpuDA_rest = [(0, 40960, 258, 257, 0, 16384, 'fcmovb', 5...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_fpuDB_00BF = [(0, 40960, 67698690, 0, 0, 16384, 'fild', ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_fpuDB_rest = [(0, 40960, 258, 257, 0, 16384, 'fcmovnb', ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_fpuDC_00BF = [(0, 40960, 537460738, 0, 0, 16384, 'fadd',...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_fpuDC_rest = [(0, 40960, 258, 257, 0, 16384, 'fadd', 54,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_fpuDD_00BF = [(0, 40960, 537460738, 0, 0, 16384, 'fld', ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_fpuDD_rest = [(0, 40960, 258, 0, 0, 16384, 'ffree', 54, ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_fpuDE_00BF = [(0, 40960, 235470850, 0, 0, 16384, 'fiadd'...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_fpuDE_rest = [(0, 40960, 258, 257, 0, 16384, 'faddp', 54...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_fpuDF_00BF = [(0, 40960, 235470850, 0, 0, 16384, 'fild',...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

tbl32_fpuDF_rest = [(0, 0, 0, 0, 0, 16384, 0, 0, 0, 0), (0, 0,...

tbl_INVALID = [(0, 0, 0, 0, 0, 0, 0, 0, 0, 0)]
### These values allow an opcode to be sliced and diced to make it fit correctly into the current lookup table.

tables86 = [([(0, 8193, 33816578, 33947649, 0, 12288, 'add', 0...

regs = [('eax', 'REG_GENERAL,REG_RET', 4), ('ecx', 'REG_GENERA...

prefix_table = {0: 0, 38: 1073741824, 46: 268435456, 54: 53687...

ADDRMETH_MASK = 16711680

OPTYPE_MASK = 4278190080

OPFLAGS_MASK = 65535

__package__ = 'envi.archs.i386'

Variables Details

[hide private]

OPERSIZE

Value:

{0: (2, 4, 8),
 16777216: (2, 4, 4),
 33554432: (1, 1, 1),
 50331648: (1, 2, 2),
 67108864: (4, 4, 4),
 83886080: (16, 16, 16),
 100663296: (4, 6, 6),
 117440512: (8, 8, 8),
...

tbl32_Main

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 8193, 33816578, 33947649, 0, 12288, 'add', 0, 0, 0),
 (0, 8193, 218365954, 218497025, 0, 12288, 'add', 0, 0, 0),
 (0, 8193, 33947650, 33816577, 0, 12288, 'add', 0, 0, 0),
 (0, 8193, 218497026, 218365953, 0, 12288, 'add', 0, 0, 0),
 (0, 8193, 258, 34017281, 0, 12288, 'add', 524288, 0, 0),
 (0, 8193, 258, 252121089, 0, 12288, 'add', 0, 0, 0),
 (0, 16385, 257, 0, 0, 12288, 'push', 48, 0, 0),
 (0, 16386, 258, 0, 0, 12288, 'pop', 48, 0, 0),
...

tbl32_0F

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(16, 0, 0, 0, 0, 12288, 0, 0, 0, 0),
 (17, 0, 0, 0, 0, 12288, 0, 0, 0, 0),
 (0, 57344, 218497026, 235143169, 0, 12288, 'lar', 0, 0, 0),
 (0, 57344, 218497026, 235143169, 0, 12288, 'lsl', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 57344, 0, 0, 0, 40960, 'syscall', 0, 0, 0),
 (0, 57344, 0, 0, 0, 12288, 'clts', 0, 0, 0),
 (0, 57344, 0, 0, 0, 40960, 'sysret', 0, 0, 0),
...

tbl32_660F

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(16, 0, 0, 0, 0, 12288, 0, 0, 0, 0),
 (17, 0, 0, 0, 0, 12288, 0, 0, 0, 0),
 (0, 57344, 218497026, 235143169, 0, 12288, 'lar', 0, 0, 0),
 (0, 57344, 218497026, 235143169, 0, 12288, 'lsl', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 57344, 0, 0, 0, 12288, 'clts', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
...

tbl32_F20F

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(16, 0, 0, 0, 0, 12288, 0, 0, 0, 0),
 (17, 0, 0, 0, 0, 12288, 0, 0, 0, 0),
 (0, 57344, 218497026, 235143169, 0, 12288, 'lar', 0, 0, 0),
 (0, 57344, 218497026, 235143169, 0, 12288, 'lsl', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 57344, 0, 0, 0, 12288, 'clts', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
...

tbl32_F30F

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(16, 0, 0, 0, 0, 12288, 0, 0, 0, 0),
 (17, 0, 0, 0, 0, 12288, 0, 0, 0, 0),
 (0, 57344, 218497026, 235143169, 0, 12288, 'lar', 0, 0, 0),
 (0, 57344, 218497026, 235143169, 0, 12288, 'lsl', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 57344, 0, 0, 0, 12288, 'clts', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
...

tbl32_0F00

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 57344, 235143169, 0, 0, 12288, 'sldt', 0, 0, 0),
 (0, 57344, 235143170, 0, 0, 12288, 'str', 0, 0, 0),
 (0, 57344, 235143170, 0, 0, 12288, 'lldt', 0, 0, 0),
 (0, 57344, 235143170, 0, 0, 12288, 'ltr', 0, 0, 0),
 (0, 57344, 235143169, 0, 0, 12288, 'verr', 0, 0, 0),
 (0, 57344, 235143169, 0, 0, 12288, 'verw', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0)]

tbl32_0F01_00BF

Value:

[(0, 57344, 168361985, 0, 0, 12288, 'sgdt', 0, 0, 0),
 (0, 57344, 168361985, 0, 0, 12288, 'sidt', 0, 0, 0),
 (0, 57344, 168361986, 0, 0, 12288, 'lgdt', 0, 0, 0),
 (0, 57344, 168361986, 0, 0, 12288, 'lidt', 0, 0, 0),
 (0, 57344, 235143170, 0, 0, 12288, 'smsw', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 57344, 235143170, 0, 0, 12288, 'lmsw', 0, 0, 0),
 (0, 57344, 34144257, 0, 0, 20480, 'invlpg', 0, 0, 0)]

tbl32_0F01_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 57344, 0, 0, 0, 36864, 'vmcall', 0, 0, 0),
 (0, 57344, 0, 0, 0, 36864, 'vmlaunch', 0, 0, 0),
 (0, 57344, 0, 0, 0, 36864, 'vmresume', 0, 0, 0),
 (0, 57344, 0, 0, 0, 36864, 'vmxoff', 0, 0, 0),
 (0, 57344, 235143170, 0, 0, 12288, 'smsw', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 57344, 235143170, 0, 0, 12288, 'lmsw', 0, 0, 0),
...

tbl32_0F18

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 57344, 589826, 0, 0, 36864, 'prefetch', 0, 0, 0),
 (0, 57344, 258, 0, 0, 36864, 'prefetch', 40, 0, 0),
 (0, 57344, 258, 0, 0, 36864, 'prefetch', 41, 0, 0),
 (0, 57344, 258, 0, 0, 36864, 'prefetch', 42, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0)]

tbl32_0F71

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 61440, 151650306, 34013185, 0, 32768, 'psrlw', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 61440, 151650306, 34013185, 0, 32768, 'psraw', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 61440, 151650306, 34013185, 0, 32768, 'psllw', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0)]

tbl32_0F72

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 61440, 151650306, 34013185, 0, 32768, 'psrld', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 61440, 151650306, 34013185, 0, 32768, 'psrad', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 61440, 151650306, 34013185, 0, 32768, 'pslld', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0)]

tbl32_0F73

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 61440, 151650306, 34013185, 0, 32768, 'psrlq', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 61440, 151650306, 34013185, 0, 32768, 'psllq', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0)]

tbl32_660F73

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 61440, 85000194, 34013185, 0, 32768, 'psrlq', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 61440, 85000194, 34013185, 0, 32768, 'psllq', 0, 0, 0),
 (0, 61440, 85000194, 34013185, 0, 32768, 'psldq', 0, 0, 0)]

tbl32_0FAE_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 40960, 218365954, 0, 0, 32768, 'fxsave', 0, 0, 0),
 (0, 40960, 218365953, 0, 0, 32768, 'fxrstor', 0, 0, 0),
 (0, 40960, 218365953, 0, 0, 36864, 'ldmxcsr', 0, 0, 0),
 (0, 40960, 218365954, 0, 0, 36864, 'stmxcsr', 0, 0, 0),
 (0, 40960, 218365954, 0, 0, 36864, 'xsave', 0, 0, 0),
 (0, 40960, 218365954, 0, 0, 36864, 'xrstor', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 40960, 33816578, 0, 0, 36864, 'clflush', 0, 0, 0)]

tbl32_0FAE_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 40960, 0, 0, 0, 36864, 'lfence', 0, 0, 0),
 (0, 40960, 0, 0, 0, 36864, 'mfence', 0, 0, 0),
 (0, 40960, 0, 0, 0, 36864, 'sfence', 0, 0, 0)]

tbl32_0FBA

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 32769, 218365953, 34013185, 0, 12288, 'bt', 0, 0, 0),
 (0, 32769, 218365953, 34013185, 0, 12288, 'bts', 0, 0, 0),
 (0, 32769, 218365953, 34013185, 0, 12288, 'btr', 0, 0, 0),
 (0, 32769, 218365953, 34013185, 0, 12288, 'btc', 0, 0, 0)]

tbl32_0FC2

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 24580, 151584770, 0, 0, 24576, 'cmpxch8b', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
...

tbl32_0FC7_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 24580, 151584770, 0, 0, 24576, 'cmpxch8b', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 57344, 151584770, 0, 0, 0, 'vmptrld', 0, 0, 0),
 (0, 57344, 151584770, 0, 0, 0, 'vmptrst', 0, 0, 0)]

tbl32_0FC7_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
...

tbl32_660FC7_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 24580, 151584770, 0, 0, 24576, 'cmpxch8b', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 57344, 151584770, 0, 0, 0, 'vmclear', 0, 0, 0),
 (0, 57344, 151584770, 0, 0, 0, 'vmptrst', 0, 0, 0)]

tbl32_660FC7_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
...

tbl32_F20FC7_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0)]

tbl32_F20FC7_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
...

tbl32_F30FC7_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 57344, 151584770, 0, 0, 0, 'vmxon', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0)]

tbl32_F30FC7_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
...

tbl32_80

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 8193, 33816578, 34017281, 0, 12288, 'add', 0, 0, 0),
 (0, 12290, 33816578, 34013185, 0, 12288, 'or', 0, 0, 0),
 (0, 8193, 33816578, 34017281, 0, 12288, 'adc', 0, 0, 0),
 (0, 8194, 33816578, 34017281, 0, 12288, 'sbb', 0, 0, 0),
 (0, 12289, 33816578, 34013185, 0, 12288, 'and', 0, 0, 0),
 (0, 8194, 33816578, 34017281, 0, 12288, 'sub', 0, 0, 0),
 (0, 12291, 33816578, 34013185, 0, 12288, 'xor', 0, 0, 0),
 (0, 20482, 33816577, 34017281, 0, 12288, 'cmp', 0, 0, 0)]

tbl32_81

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 8193, 218365954, 252121089, 0, 12288, 'add', 0, 0, 0),
 (0, 12290, 218365954, 252116993, 0, 12288, 'or', 0, 0, 0),
 (0, 8193, 218365954, 252121089, 0, 12288, 'adc', 0, 0, 0),
 (0, 8194, 218365954, 252121089, 0, 12288, 'sbb', 0, 0, 0),
 (0, 12289, 218365954, 252116993, 0, 12288, 'and', 0, 0, 0),
 (0, 8194, 218365954, 252121089, 0, 12288, 'sub', 0, 0, 0),
 (0, 12291, 218365954, 252116993, 0, 12288, 'xor', 0, 0, 0),
 (0, 20482, 218365953, 252121089, 0, 12288, 'cmp', 0, 0, 0)]

tbl32_82

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 8193, 33816578, 34017281, 0, 12288, 'add', 0, 0, 0),
 (0, 12290, 33816578, 34013185, 0, 12288, 'or', 0, 0, 0),
 (0, 8193, 33816578, 34017281, 0, 12288, 'adc', 0, 0, 0),
 (0, 8194, 33816578, 34017281, 0, 12288, 'sbb', 0, 0, 0),
 (0, 12289, 33816578, 34013185, 0, 12288, 'and', 0, 0, 0),
 (0, 8194, 33816578, 34017281, 0, 12288, 'sub', 0, 0, 0),
 (0, 12291, 33816578, 34013185, 0, 12288, 'xor', 0, 0, 0),
 (0, 20482, 33816577, 34017281, 0, 12288, 'cmp', 0, 0, 0)]

tbl32_83

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 8193, 218365954, 34017281, 0, 12288, 'add', 0, 0, 0),
 (0, 12290, 218365954, 34017281, 0, 12288, 'or', 0, 0, 0),
 (0, 8193, 218365954, 34017281, 0, 12288, 'adc', 0, 0, 0),
 (0, 8194, 218365954, 34017281, 0, 12288, 'sbb', 0, 0, 0),
 (0, 12289, 218365954, 34013185, 0, 12288, 'and', 0, 0, 0),
 (0, 8194, 218365954, 34017281, 0, 12288, 'sub', 0, 0, 0),
 (0, 12291, 218365954, 34013185, 0, 12288, 'xor', 0, 0, 0),
 (0, 20482, 218365953, 34017281, 0, 12288, 'cmp', 0, 0, 0)]

tbl32_C0

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 8201, 33816578, 34013185, 0, 12288, 'rol', 0, 0, 0),
 (0, 8202, 33816578, 34013185, 0, 12288, 'ror', 0, 0, 0),
 (0, 8201, 33816578, 34013185, 0, 12288, 'rcl', 0, 0, 0),
 (0, 8202, 33816578, 34013185, 0, 12288, 'rcr', 0, 0, 0),
 (0, 8199, 33816578, 34013185, 0, 12288, 'shl', 0, 0, 0),
 (0, 8200, 33816578, 34013185, 0, 12288, 'shr', 0, 0, 0),
 (0, 8199, 33816578, 34013185, 0, 12288, 'sal', 0, 0, 0),
 (0, 8200, 33816578, 34013185, 0, 12288, 'sar', 0, 0, 0)]

tbl32_C1

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 8201, 218365954, 34013185, 0, 12288, 'rol', 0, 0, 0),
 (0, 8202, 218365954, 34013185, 0, 12288, 'ror', 0, 0, 0),
 (0, 8201, 218365954, 34013185, 0, 12288, 'rcl', 0, 0, 0),
 (0, 8202, 218365954, 34013185, 0, 12288, 'rcr', 0, 0, 0),
 (0, 8199, 218365954, 34013185, 0, 12288, 'shl', 0, 0, 0),
 (0, 8200, 218365954, 34013185, 0, 12288, 'shr', 0, 0, 0),
 (0, 8199, 218365954, 34013185, 0, 12288, 'sal', 0, 0, 0),
 (0, 8200, 218365954, 34013185, 0, 12288, 'sar', 0, 0, 0)]

tbl32_D0

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 8201, 33816578, 513, 0, 12288, 'rol', 0, 1, 0),
 (0, 8202, 33816578, 513, 0, 12288, 'ror', 0, 1, 0),
 (0, 8201, 33816578, 513, 0, 12288, 'rcl', 0, 1, 0),
 (0, 8202, 33816578, 513, 0, 12288, 'rcr', 0, 1, 0),
 (0, 8199, 33816578, 513, 0, 12288, 'shl', 0, 1, 0),
 (0, 8200, 33816578, 513, 0, 12288, 'shr', 0, 1, 0),
 (0, 8199, 33816578, 513, 0, 12288, 'sal', 0, 1, 0),
 (0, 8200, 33816578, 513, 0, 12288, 'sar', 0, 1, 0)]

tbl32_D1

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 8201, 218365954, 513, 0, 12288, 'rol', 0, 1, 0),
 (0, 8202, 218365954, 513, 0, 12288, 'ror', 0, 1, 0),
 (0, 8201, 218365954, 513, 0, 12288, 'rcl', 0, 1, 0),
 (0, 8202, 218365954, 513, 0, 12288, 'rcr', 0, 1, 0),
 (0, 8199, 218365954, 513, 0, 12288, 'shl', 0, 1, 0),
 (0, 8200, 218365954, 513, 0, 12288, 'shr', 0, 1, 0),
 (0, 8199, 218365954, 513, 0, 12288, 'sal', 0, 1, 0),
 (0, 8200, 218365954, 513, 0, 12288, 'sar', 0, 1, 0)]

tbl32_D2

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 8201, 33816578, 257, 0, 12288, 'rol', 0, 524289, 0),
 (0, 8202, 33816578, 257, 0, 12288, 'ror', 0, 524289, 0),
 (0, 8201, 33816578, 257, 0, 12288, 'rcl', 0, 524289, 0),
 (0, 8202, 33816578, 257, 0, 12288, 'rcr', 0, 524289, 0),
 (0, 8199, 33816578, 257, 0, 12288, 'shl', 0, 524289, 0),
 (0, 8200, 33816578, 257, 0, 12288, 'shr', 0, 524289, 0),
 (0, 8199, 33816578, 257, 0, 12288, 'sal', 0, 524289, 0),
 (0, 8200, 33816578, 257, 0, 12288, 'sar', 0, 524289, 0)]

tbl32_D3

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 8201, 218365954, 257, 0, 12288, 'rol', 0, 524289, 0),
 (0, 8202, 218365954, 257, 0, 12288, 'ror', 0, 524289, 0),
 (0, 8201, 218365954, 257, 0, 12288, 'rcl', 0, 524289, 0),
 (0, 8202, 218365954, 257, 0, 12288, 'rcr', 0, 524289, 0),
 (0, 8199, 218365954, 257, 0, 12288, 'shl', 0, 524289, 0),
 (0, 8200, 218365954, 257, 0, 12288, 'shr', 0, 524289, 0),
 (0, 8199, 218365954, 257, 0, 12288, 'sal', 0, 524289, 0),
 (0, 8200, 218365954, 257, 0, 12288, 'sar', 0, 524289, 0)]

tbl32_F6

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 20481, 33816577, 34017281, 0, 12288, 'test', 0, 0, 0),
 (0, 20481, 33816577, 34017281, 0, 12288, 'test', 0, 0, 0),
 (0, 12292, 33816578, 0, 0, 12288, 'not', 0, 0, 0),
 (0, 12293, 33816578, 0, 0, 12288, 'neg', 0, 0, 0),
 (0, 8195, 258, 33816577, 0, 12288, 'mul', 524288, 0, 0),
 (0, 8195, 258, 33816577, 0, 12288, 'imul', 524288, 0, 0),
 (0, 8196, 258, 33816577, 0, 12288, 'div', 524288, 0, 0),
 (0, 8196, 33816577, 0, 0, 12288, 'idiv', 524288, 0, 0)]

tbl32_F7

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 20481, 218365953, 252116993, 0, 12288, 'test', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 12292, 218365954, 0, 0, 12288, 'not', 0, 0, 0),
 (0, 12293, 218365954, 0, 0, 12288, 'neg', 0, 0, 0),
 (0, 8195, 258, 218365953, 0, 12288, 'mul', 0, 0, 0),
 (0, 8195, 258, 218365953, 0, 12288, 'imul', 0, 0, 0),
 (0, 8196, 258, 218365953, 0, 12288, 'div', 0, 0, 0),
 (0, 8196, 218365953, 0, 0, 12288, 'idiv', 0, 0, 0)]

tbl32_FE

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 8197, 33816578, 0, 0, 12288, 'inc', 0, 0, 0),
 (0, 8198, 33816578, 0, 0, 12288, 'dec', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0)]

tbl32_FF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 8197, 218365954, 0, 0, 12288, 'inc', 0, 0, 0),
 (0, 8198, 218365954, 0, 0, 12288, 'dec', 0, 0, 0),
 (0, 4099, 218365956, 0, 0, 12288, 'call', 0, 0, 0),
 (0, 4099, 100925444, 0, 0, 12288, 'call', 0, 0, 0),
 (0, 4097, 218365956, 0, 0, 12288, 'jmp', 0, 0, 0),
 (0, 4097, 100925444, 0, 0, 12288, 'jmp', 0, 0, 0),
 (0, 16385, 218365953, 0, 0, 12288, 'push', 0, 0, 0),
 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0)]

tbl32_fpuD8_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 40960, 269025282, 0, 0, 16384, 'fadd', 0, 0, 0),
 (0, 40960, 269025282, 0, 0, 16384, 'fmul', 0, 0, 0),
 (0, 40960, 269025282, 0, 0, 16384, 'fcom', 0, 0, 0),
 (0, 40960, 269025282, 0, 0, 16384, 'fcomp', 0, 0, 0),
 (0, 40960, 269025282, 0, 0, 16384, 'fsub', 0, 0, 0),
 (0, 40960, 269025282, 0, 0, 16384, 'fsubr', 0, 0, 0),
 (0, 40960, 269025282, 0, 0, 16384, 'fdiv', 0, 0, 0),
 (0, 40960, 269025282, 0, 0, 16384, 'fdivr', 0, 0, 0)]

tbl32_fpuD8_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 40960, 258, 257, 0, 16384, 'fadd', 54, 54, 0),
 (0, 40960, 258, 257, 0, 16384, 'fadd', 54, 55, 0),
 (0, 40960, 258, 257, 0, 16384, 'fadd', 54, 56, 0),
 (0, 40960, 258, 257, 0, 16384, 'fadd', 54, 57, 0),
 (0, 40960, 258, 257, 0, 16384, 'fadd', 54, 58, 0),
 (0, 40960, 258, 257, 0, 16384, 'fadd', 54, 59, 0),
 (0, 40960, 258, 257, 0, 16384, 'fadd', 54, 60, 0),
 (0, 40960, 258, 257, 0, 16384, 'fadd', 54, 61, 0),
...

tbl32_fpuD9_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 40960, 269025282, 0, 0, 16384, 'fld', 0, 0, 0),
 (0, 0, 0, 0, 0, 16384, 0, 0, 0, 0),
 (0, 40960, 269025282, 0, 0, 16384, 'fst', 0, 0, 0),
 (0, 40960, 269025282, 0, 0, 16384, 'fstp', 0, 0, 0),
 (0, 40960, 1342767106, 0, 0, 16384, 'fldenv', 0, 0, 0),
 (0, 40960, 235470850, 0, 0, 16384, 'fldcw', 0, 0, 0),
 (0, 40960, 1342767106, 0, 0, 16384, 'fstenv', 0, 0, 0),
 (0, 40960, 235470850, 0, 0, 16384, 'fstcw', 0, 0, 0)]

tbl32_fpuD9_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 40960, 258, 257, 0, 16384, 'fld', 54, 54, 0),
 (0, 40960, 258, 257, 0, 16384, 'fld', 54, 55, 0),
 (0, 40960, 258, 257, 0, 16384, 'fld', 54, 56, 0),
 (0, 40960, 258, 257, 0, 16384, 'fld', 54, 57, 0),
 (0, 40960, 258, 257, 0, 16384, 'fld', 54, 58, 0),
 (0, 40960, 258, 257, 0, 16384, 'fld', 54, 59, 0),
 (0, 40960, 258, 257, 0, 16384, 'fld', 54, 60, 0),
 (0, 40960, 258, 257, 0, 16384, 'fld', 54, 61, 0),
...

tbl32_fpuDA_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 40960, 67698690, 0, 0, 16384, 'fiadd', 0, 0, 0),
 (0, 40960, 67698690, 0, 0, 16384, 'fimul', 0, 0, 0),
 (0, 40960, 67698690, 0, 0, 16384, 'ficom', 0, 0, 0),
 (0, 40960, 67698690, 0, 0, 16384, 'ficomp', 0, 0, 0),
 (0, 40960, 67698690, 0, 0, 16384, 'fisub', 0, 0, 0),
 (0, 40960, 67698690, 0, 0, 16384, 'fisubr', 0, 0, 0),
 (0, 40960, 67698690, 0, 0, 16384, 'fidiv', 0, 0, 0),
 (0, 40960, 67698690, 0, 0, 16384, 'fidivr', 0, 0, 0)]

tbl32_fpuDA_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 40960, 258, 257, 0, 16384, 'fcmovb', 54, 54, 0),
 (0, 40960, 258, 257, 0, 16384, 'fcmovb', 54, 55, 0),
 (0, 40960, 258, 257, 0, 16384, 'fcmovb', 54, 56, 0),
 (0, 40960, 258, 257, 0, 16384, 'fcmovb', 54, 57, 0),
 (0, 40960, 258, 257, 0, 16384, 'fcmovb', 54, 58, 0),
 (0, 40960, 258, 257, 0, 16384, 'fcmovb', 54, 59, 0),
 (0, 40960, 258, 257, 0, 16384, 'fcmovb', 54, 60, 0),
 (0, 40960, 258, 257, 0, 16384, 'fcmovb', 54, 61, 0),
...

tbl32_fpuDB_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 40960, 67698690, 0, 0, 16384, 'fild', 0, 0, 0),
 (0, 0, 0, 0, 0, 16384, 0, 0, 0, 0),
 (0, 40960, 67698690, 0, 0, 16384, 'fist', 0, 0, 0),
 (0, 40960, 67698690, 0, 0, 16384, 'fistp', 0, 0, 0),
 (0, 0, 0, 0, 0, 16384, 0, 0, 0, 0),
 (0, 40960, 805896194, 0, 0, 16384, 'fld', 0, 0, 0),
 (0, 0, 0, 0, 0, 16384, 0, 0, 0, 0),
 (0, 40960, 805896194, 0, 0, 16384, 'fstp', 0, 0, 0)]

tbl32_fpuDB_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 40960, 258, 257, 0, 16384, 'fcmovnb', 54, 54, 0),
 (0, 40960, 258, 257, 0, 16384, 'fcmovnb', 54, 55, 0),
 (0, 40960, 258, 257, 0, 16384, 'fcmovnb', 54, 56, 0),
 (0, 40960, 258, 257, 0, 16384, 'fcmovnb', 54, 57, 0),
 (0, 40960, 258, 257, 0, 16384, 'fcmovnb', 54, 58, 0),
 (0, 40960, 258, 257, 0, 16384, 'fcmovnb', 54, 59, 0),
 (0, 40960, 258, 257, 0, 16384, 'fcmovnb', 54, 60, 0),
 (0, 40960, 258, 257, 0, 16384, 'fcmovnb', 54, 61, 0),
...

tbl32_fpuDC_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 40960, 537460738, 0, 0, 16384, 'fadd', 0, 0, 0),
 (0, 40960, 537460738, 0, 0, 16384, 'fmul', 0, 0, 0),
 (0, 40960, 537460738, 0, 0, 16384, 'fcom', 0, 0, 0),
 (0, 40960, 537460738, 0, 0, 16384, 'fcomp', 0, 0, 0),
 (0, 40960, 537460738, 0, 0, 16384, 'fsub', 0, 0, 0),
 (0, 40960, 537460738, 0, 0, 16384, 'fsubr', 0, 0, 0),
 (0, 40960, 537460738, 0, 0, 16384, 'fdiv', 0, 0, 0),
 (0, 40960, 537460738, 0, 0, 16384, 'fdivr', 0, 0, 0)]

tbl32_fpuDC_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 40960, 258, 257, 0, 16384, 'fadd', 54, 54, 0),
 (0, 40960, 258, 257, 0, 16384, 'fadd', 55, 54, 0),
 (0, 40960, 258, 257, 0, 16384, 'fadd', 56, 54, 0),
 (0, 40960, 258, 257, 0, 16384, 'fadd', 57, 54, 0),
 (0, 40960, 258, 257, 0, 16384, 'fadd', 58, 54, 0),
 (0, 40960, 258, 257, 0, 16384, 'fadd', 59, 54, 0),
 (0, 40960, 258, 257, 0, 16384, 'fadd', 60, 54, 0),
 (0, 40960, 258, 257, 0, 16384, 'fadd', 61, 54, 0),
...

tbl32_fpuDD_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 40960, 537460738, 0, 0, 16384, 'fld', 0, 0, 0),
 (0, 0, 0, 0, 0, 16384, 0, 0, 0, 0),
 (0, 40960, 537460738, 0, 0, 16384, 'fst', 0, 0, 0),
 (0, 40960, 537460738, 0, 0, 16384, 'fstp', 0, 0, 0),
 (0, 40960, 1342767106, 0, 0, 16384, 'frstor', 0, 0, 0),
 (0, 0, 0, 0, 0, 16384, 0, 0, 0, 0),
 (0, 40960, 1342767106, 0, 0, 16384, 'fsave', 0, 0, 0),
 (0, 40960, 235470850, 0, 0, 16384, 'fstsw', 0, 0, 0)]

tbl32_fpuDD_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 40960, 258, 0, 0, 16384, 'ffree', 54, 0, 0),
 (0, 40960, 258, 0, 0, 16384, 'ffree', 55, 0, 0),
 (0, 40960, 258, 0, 0, 16384, 'ffree', 56, 0, 0),
 (0, 40960, 258, 0, 0, 16384, 'ffree', 57, 0, 0),
 (0, 40960, 258, 0, 0, 16384, 'ffree', 58, 0, 0),
 (0, 40960, 258, 0, 0, 16384, 'ffree', 59, 0, 0),
 (0, 40960, 258, 0, 0, 16384, 'ffree', 60, 0, 0),
 (0, 40960, 258, 0, 0, 16384, 'ffree', 61, 0, 0),
...

tbl32_fpuDE_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 40960, 235470850, 0, 0, 16384, 'fiadd', 0, 0, 0),
 (0, 40960, 235470850, 0, 0, 16384, 'fimul', 0, 0, 0),
 (0, 40960, 235470850, 0, 0, 16384, 'ficom', 0, 0, 0),
 (0, 40960, 235470850, 0, 0, 16384, 'ficomp', 0, 0, 0),
 (0, 40960, 235470850, 0, 0, 16384, 'fisub', 0, 0, 0),
 (0, 40960, 235470850, 0, 0, 16384, 'fisubr', 0, 0, 0),
 (0, 40960, 235470850, 0, 0, 16384, 'fidiv', 0, 0, 0),
 (0, 40960, 235470850, 0, 0, 16384, 'fidivr', 0, 0, 0)]

tbl32_fpuDE_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 40960, 258, 257, 0, 16384, 'faddp', 54, 54, 0),
 (0, 40960, 258, 257, 0, 16384, 'faddp', 55, 54, 0),
 (0, 40960, 258, 257, 0, 16384, 'faddp', 56, 54, 0),
 (0, 40960, 258, 257, 0, 16384, 'faddp', 57, 54, 0),
 (0, 40960, 258, 257, 0, 16384, 'faddp', 58, 54, 0),
 (0, 40960, 258, 257, 0, 16384, 'faddp', 59, 54, 0),
 (0, 40960, 258, 257, 0, 16384, 'faddp', 60, 54, 0),
 (0, 40960, 258, 257, 0, 16384, 'faddp', 61, 54, 0),
...

tbl32_fpuDF_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:

[(0, 40960, 235470850, 0, 0, 16384, 'fild', 0, 0, 0),
 (0, 40960, 235470850, 0, 0, 16384, 'fisttp', 0, 0, 0),
 (0, 40960, 235470850, 0, 0, 16384, 'fist', 0, 0, 0),
 (0, 40960, 235470850, 0, 0, 16384, 'fistp', 0, 0, 0),
 (0, 40960, 1074331650, 0, 0, 16384, 'fbld', 0, 0, 0),
 (0, 40960, 151584770, 0, 0, 16384, 'fild', 0, 0, 0),
 (0, 40960, 1074331650, 0, 0, 16384, 'fbstp', 0, 0, 0),
 (0, 40960, 151584770, 0, 0, 16384, 'fistp', 0, 0, 0)]

tbl32_fpuDF_rest

Value:

[(0, 0, 0, 0, 0, 16384, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 16384, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 16384, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 16384, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 16384, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 16384, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 16384, 0, 0, 0, 0),
 (0, 0, 0, 0, 0, 16384, 0, 0, 0, 0),
...

tbl_INVALID

### These values allow an opcode to be sliced and diced to make it fit correctly into the current lookup table. # # (tbl32_0F, 0, 0xff, 0, 0xff), # (tbl32_80, 3, 0x07, 0, 0xff, 4), # # Table pointer # shift bits right (eg. >> 4 makes each line in the table valid for 16 numbers... ie 0xc0-0xcf are all one entry in the table) # mask part of the byte (eg. & 0x7 only makes use of the 00000111 bits...) # simple subtraction # highest acceptable value # tables86 entry to handle the falloff (from the previous check)

Value:

[(0, 0, 0, 0, 0, 0, 0, 0, 0, 0)]

tables86

Value:

[([(0, 8193, 33816578, 33947649, 0, 12288, 'add', 0, 0, 0),
   (0, 8193, 218365954, 218497025, 0, 12288, 'add', 0, 0, 0),
   (0, 8193, 33947650, 33816577, 0, 12288, 'add', 0, 0, 0),
   (0, 8193, 218497026, 218365953, 0, 12288, 'add', 0, 0, 0),
   (0, 8193, 258, 34017281, 0, 12288, 'add', 524288, 0, 0),
   (0, 8193, 258, 252121089, 0, 12288, 'add', 0, 0, 0),
   (0, 16385, 257, 0, 0, 12288, 'push', 48, 0, 0),
   (0, 16386, 258, 0, 0, 12288, 'pop', 48, 0, 0),
...

regs

Value:

[('eax', 'REG_GENERAL,REG_RET', 4),
 ('ecx', 'REG_GENERAL,REG_COUNT', 4),
 ('edx', 'REG_GENERAL', 4),
 ('ebx', 'REG_GENERAL', 4),
 ('esp', 'REG_SP', 4),
 ('ebp', 'REG_GENERAL,REG_FP', 4),
 ('esi', 'REG_GENERAL,REG_SRC', 4),
 ('edi', 'REG_GENERAL,REG_DEST', 4),
...

prefix_table

Value:

{0: 0,
 38: 1073741824,
 46: 268435456,
 54: 536870912,
 62: 805306368,
 100: 1342177280,
 101: 1610612736,
 102: 33554432,
...