Package envi :: Package archs :: Package arm :: Module emu
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Module emu

source code

The initial arm module.

Classes [hide private]
  ArmArchitectureProcedureCall
Implement calling conventions for your arch.
  CoProcEmulator
  ArmEmulator
Variables [hide private]
  aapcs = ArmArchitectureProcedureCall()
  opcode_dist = [('and', 4083), ('stm', 1120), ('ldr', 1064), ('...
  ArmMeta = (('N', 16, 31, 1), ('Z', 16, 30, 1), ('C', 16, 29, 1...
  COND_AL = 14
  COND_CC = 3
  COND_CS = 2
  COND_EQ = 0
  COND_EXTENDED = 15
  COND_GE = 10
  COND_GT = 12
  COND_HI = 8
  COND_LE = 13
  COND_LO = 9
  COND_LT = 11
  COND_MI = 4
  COND_NE = 1
  COND_PL = 5
  COND_VC = 7
  COND_VS = 6
  IENC_ARCH_UNDEF = 10
  IENC_BRANCH = 13
  IENC_COPROC_DP = 16
  IENC_COPROC_LOAD = 15
  IENC_COPROC_REG_XFER = 17
  IENC_COPROC_RREG_XFER = 14
  IENC_DP_IMM = 7
  IENC_DP_IMM_SHIFT = 0
  IENC_DP_REG_SHIFT = 3
  IENC_EXTRA_LOAD = 20
  IENC_LOAD_IMM_OFF = 8
  IENC_LOAD_MULT = 12
  IENC_LOAD_REG_OFF = 9
  IENC_MEDIA = 11
  IENC_MEDIA_EXTEND = 722688
  IENC_MEDIA_PARALLEL = 721152
  IENC_MEDIA_REV = 721664
  IENC_MEDIA_SAT = 721408
  IENC_MEDIA_SEL = 721920
  IENC_MEDIA_USAD8 = 722176
  IENC_MEDIA_USADA8 = 722432
  IENC_MISC = 1
  IENC_MISC1 = 2
  IENC_MOV_IMM_STAT = 6
  IENC_MULT = 4
  IENC_SWINT = 18
  IENC_UNCOND = 19
  IENC_UNCOND_BLX = 1246208
  IENC_UNCOND_CPS = 1245440
  IENC_UNCOND_PLD = 1245952
  IENC_UNCOND_SETEND = 1245696
  IENC_UNDEF = 5
  IF_B = 512
  IF_D = 8192
  IF_DA = 8388608
  IF_DAIB_B = 41943040
  IF_DAIB_I = 25165824
  IF_DAIB_MASK = 58720256
  IF_DAIB_SHFT = 23
  IF_DB = 41943040
  IF_H = 2048
  IF_IA = 25165824
  IF_IB = 58720256
  IF_L = 16384
  IF_PSR_S = 256
  IF_S = 4096
  IF_T = 32768
  IF_UM = 131072
  IF_W = 65536
  INST_ENC_DP_IMM = 0
  INST_ENC_MISC = 1
  INS_B = 851968
  INS_BL = 851969
  INS_BLX = 1246208
  INS_BX = 65539
  INS_BXJ = 65541
  MODE_ARM = 0
  MODE_JAZELLE = 2
  MODE_THUMB = 1
  OF_UM = 512
  OF_W = 256
  OSZFMT_BYTE = 'B'
  OSZFMT_HWORD = '<H'
  OSZFMT_WORD = '<L'
  OSZ_BYTE = 1
  OSZ_HWORD = 2
  OSZ_WORD = 4
  O_IMM = 1
  O_REG = 0
  OperType = ArmRegOper, ArmImmOper,
  PM_abt = 23
  PM_fiq = 17
  PM_irq = 18
  PM_svc = 19
  PM_sys = 31
  PM_und = 27
  PM_usr = 16
  PSR_A = 8
  PSR_C = 29
  PSR_C_bit = 536870912
  PSR_C_mask = 3758096383
  PSR_E = 9
  PSR_F = 6
  PSR_GE = 16
  PSR_I = 7
  PSR_J = 24
  PSR_M = 0
  PSR_N = 31
  PSR_Q = 27
  PSR_T = 5
  PSR_V = 28
  PSR_Z = 30
  REG_BP = None
hash(x)
  REG_CPSR = 16
  REG_FLAGS = 16
  REG_FP = 11
  REG_IP = 12
  REG_LR = 14
  REG_OFFSET_ABT = 119
  REG_OFFSET_CPSR = 16
  REG_OFFSET_FIQ = 17
  REG_OFFSET_IRQ = 34
  REG_OFFSET_SVC = 51
  REG_OFFSET_SYS = 255
  REG_OFFSET_UND = 187
  REG_OFFSET_USR = 0
  REG_PC = 15
  REG_R0 = 0
  REG_R1 = 1
  REG_R2 = 2
  REG_R3 = 3
  REG_R4 = 4
  REG_R5 = 5
  REG_R6 = 6
  REG_R7 = 7
  REG_R8 = 8
  REG_R9 = 9
  REG_SL = 10
  REG_SP = 13
  REG_SPSR_abt = 135
  REG_SPSR_fiq = 33
  REG_SPSR_irq = 50
  REG_SPSR_svc = 67
  REG_SPSR_sys = 271
  REG_SPSR_und = 203
  REG_SPSR_usr = 16
  SOT_IMM = 1
  SOT_REG = 0
  S_ASR = 2
  S_LSL = 0
  S_LSR = 1
  S_ROR = 3
  S_RRX = 4
  __package__ = 'envi.archs.arm'
  aif_flags = (None, 'f', 'i', 'if', 'a', 'af', 'ai', 'aif')
  arm_regs = (('r0', 32), ('r1', 32), ('r2', 32), ('r3', 32), ('...
  b_mnem = ('b', 'bl')
  binstr = '11111'
  cdp_mnem = ['cdp', 'cdp', 'cdp', 'cdp', 'cdp', 'cdp', 'cdp', '...
  cond_codes = {0: 'eq', 1: 'ne', 2: 'cs', 3: 'cc', 4: 'mi', 5: ...
  cps_mnem = ('cps', 'cps FAIL-bad encoding', 'cpsie', 'cpsid')
  daib = ('da', 'ia', 'db', 'ib')
  dp_mnem = ('and', 'eor', 'sub', 'rsb', 'add', 'adc', 'sbc', 'r...
  dp_noRd = (8, 9, 10, 11)
  dp_noRn = (13, 15)
  endian_names = ('le', 'be')
  fmts = [None, 1, 2, None, 4]
  ienc_parsers = tuple(ienc_parsers_tmp)
  ienc_parsers_tmp = [None for x in range(21)]
  iencmul_codes = {9: ('mul', (0, 4, 2), 0), 25: ('mul', (0, 4, ...
  imm11 = simpleops((O_IMM, 11, 0x7ff))
  imm3_rn_rd = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_IM...
  imm5_rm_rd = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_IM...
  imm8 = simpleops((O_IMM, 8, 0xff))
  imm8_rd = simpleops((O_REG, 8, 0x7), (O_IMM, 0, 0xff))
  inittable = [(None, ((16, 0, 0), (26214416, 16777216, 1), (262...
  l = {'ArmMeta': (('N', 16, 31, 1), ('Z', 16, 30, 1), ('C', 16,...
  ldc2_mnem = ('stc2', 'ldc2')
  ldc_mnem = ('stc', 'ldc')
  ldm_mnem = ('stm', 'ldm')
  ldr_mnem = ('str', 'ldr')
  ldrd_mnem = (('ldr', 8192), ('str', 8192))
  ldrs_mnem = (('ldr', 6144), ('ldr', 4608))
  mcr2_mnem = ('mcr2', 'mrc2')
  mcr_mnem = ('mcr', 'mrc')
  mcrr2_mnem = ('mcrr2', 'mrrc2')
  mcrr_mnem = ('mcrr', 'mrrc')
  multfail = (None, None, None)
  opinfo = (86, 'blx', <envi.archs.arm.thumbdisasm.simpleops ins...
  par_prefixes = ('', 's', 'q', 'sh', '', 'u', 'uq', 'uh')
  par_suffixes = ('add16', 'addsubx', 'subaddx', 'sub16', 'add8'...
  parallel_mnem = ('add16', 'addsubx', 'subaddx', 'sub16', 'add8...
  pkh_mnem = ('pkhbt', 'pkhtb')
  pre = 'u'
  proc_modes = {16: ('User Processor Mode', 'usr', 'Normal progr...
  psr_fields = ['M', None, None, None, None, 'T', 'F', 'I', 'A',...
  psrs = ('CPSR', 'SPSR')
  qop_mnem = ('qadd', 'qsub', 'qdadd', 'qdsub')
  rev_mnem = ('rev', 'rev16', None, 'revsh')
  rm4_shift3 = simpleops((O_REG, 3, 0xf))
  rm_rd = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7))
  rm_rd_imm0 = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_IM...
  rm_rdn = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7))
  rm_rn_rd = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_REG,...
  rn_rdm = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7))
  s_0_table = ((16, 0, 0), (26214416, 16777216, 1), (26214544, 1...
  s_1_table = ((26738688, 16777216, 5), (26738688, 18874368, 6),...
  s_3_table = ((32506096, 32506096, 10), (16, 16, 11), (0, 0, 9))
  s_6_table = ((266338304, 205520896, 14), (234881024, 201326592...
  s_7_table = ((16777216, 16777216, 18), (16777232, 16, 17), (0,...
  sat16_mnem = ('ssat16', 'usat16')
  sat_mnem = ('ssat', 'usat')
  sh4_imm1 = simpleops((O_IMM, 3, 0x1))
  shift_names = ('lsl', 'lsr', 'asr', 'ror', 'rrx')
  shifters = sh_lsl, sh_lsr, sh_asr, sh_ror, sh_rrx,
  smla_mnem = ('smlabb', 'smlabt', 'smlatb', 'smlatt')
  smlal_mnem = ('smlalbb', 'smlalbt', 'smlaltb', 'smlaltt')
  smlaw_mnem = ('smulwb', 'smulwt')
  smul_mnem = ('smulbb', 'smulbt', 'smultb', 'smultt')
  strex_mnem = ('strex', 'ldrex')
  strh_mnem = (('str', 2048), ('ldr', 2048))
  suf = 'xth'
  swap_mnem = ('swp', 'swpb')
  thumb32mask = 31
  thumb32min = 28
  thumb_32 = [29, 30, 31]
  thumb_table = [('00000', (0, 'lsl', <envi.archs.arm.thumbdisas...
  tsizes = (4, 1)
  ttree = e_btree.BinaryTree()
  x = 20
  xtnd_mnem = ('sxtab16', 'sxtab', 'sxtah', 'sxtb16', 'sxtb', 's...
  xtnd_prefixes = ('s', 'u')
  xtnd_suffixes = ('xtab16', 'xtab', 'xtah', 'xtb16', 'xtb', 'xth')
Variables Details [hide private]

opcode_dist

Value:
[('and', 4083),
 ('stm', 1120),
 ('ldr', 1064),
 ('add', 917),
 ('stc', 859),
 ('str', 770),
 ('bl', 725),
 ('ldm', 641),
...

ArmMeta

Value:
(('N', 16, 31, 1),
 ('Z', 16, 30, 1),
 ('C', 16, 29, 1),
 ('V', 16, 28, 1),
 ('Q', 16, 27, 1),
 ('J', 16, 24, 1),
 ('GE', 16, 16, 4),
 ('E', 16, 9, 1),
...

arm_regs

Value:
(('r0', 32),
 ('r1', 32),
 ('r2', 32),
 ('r3', 32),
 ('r4', 32),
 ('r5', 32),
 ('r6', 32),
 ('r7', 32),
...

cdp_mnem

Value:
['cdp',
 'cdp',
 'cdp',
 'cdp',
 'cdp',
 'cdp',
 'cdp',
 'cdp',
...

cond_codes

Value:
{0: 'eq',
 1: 'ne',
 2: 'cs',
 3: 'cc',
 4: 'mi',
 5: 'pl',
 6: 'vs',
 7: 'vc',
...

dp_mnem

Value:
('and',
 'eor',
 'sub',
 'rsb',
 'add',
 'adc',
 'sbc',
 'rsc',
...

iencmul_codes

Value:
{9: ('mul', (0, 4, 2), 0),
 25: ('mul', (0, 4, 2), 256),
 41: ('mla', (0, 4, 2, 1), 0),
 57: ('mla', (0, 4, 2, 1), 256),
 73: ('umaal', (1, 0, 4, 2), 0),
 137: ('umull', (1, 0, 4, 2), 0),
 153: ('umull', (1, 0, 4, 2), 256),
 169: ('umlal', (1, 0, 4, 2), 0),
...

imm3_rn_rd

Value:
simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_IMM, 6, 0x7))

imm5_rm_rd

Value:
simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_IMM, 6, 0x1f))

inittable

Value:
[(None,
  ((16, 0, 0),
   (26214416, 16777216, 1),
   (26214544, 16777232, 2),
   (16777456, 144, 4),
   (18874512, 18874512, 20),
   (144, 144, 20),
   (144, 16, 3),
...

l

Value:
{'ArmMeta': (('N', 16, 31, 1),
             ('Z', 16, 30, 1),
             ('C', 16, 29, 1),
             ('V', 16, 28, 1),
             ('Q', 16, 27, 1),
             ('J', 16, 24, 1),
             ('GE', 16, 16, 4),
             ('E', 16, 9, 1),
...

opinfo

Value:
(86,
 'blx',
 <envi.archs.arm.thumbdisasm.simpleops instance at 0x29f6320>,
 0)

par_suffixes

Value:
('add16', 'addsubx', 'subaddx', 'sub16', 'add8', 'sub8', '', '')

parallel_mnem

Value:
('add16',
 'addsubx',
 'subaddx',
 'sub16',
 'add8',
 'sub8',
 '',
 '',
...

proc_modes

Value:
{16: ('User Processor Mode',
      'usr',
      'Normal program execution mode',
      0,
      15,
      16),
 17: ('FIQ Processor Mode',
      'fiq',
...

psr_fields

Value:
['M',
 None,
 None,
 None,
 None,
 'T',
 'F',
 'I',
...

rm_rd_imm0

Value:
simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_IMM, 0, 0))

rm_rn_rd

Value:
simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_REG, 6, 0x7))

s_0_table

Value:
((16, 0, 0),
 (26214416, 16777216, 1),
 (26214544, 16777232, 2),
 (16777456, 144, 4),
 (18874512, 18874512, 20),
 (144, 144, 20),
 (144, 16, 3),
 (0, 0, 5))

s_1_table

Value:
((26738688, 16777216, 5), (26738688, 18874368, 6), (0, 0, 7))

s_6_table

Value:
((266338304, 205520896, 14), (234881024, 201326592, 15))

s_7_table

Value:
((16777216, 16777216, 18), (16777232, 16, 17), (0, 0, 16))

thumb_table

Value:
[('00000',
  (0,
   'lsl',
   <envi.archs.arm.thumbdisasm.simpleops instance at 0x29e8e60>,
   0)),
 ('00001',
  (1,
   'lsr',
...

xtnd_mnem

Value:
('sxtab16',
 'sxtab',
 'sxtah',
 'sxtb16',
 'sxtb',
 'sxth',
 'uxtab16',
 'uxtab',
...