envi.archs.arm.disasm

Module disasm

Variables

[hide private]

ArmMeta = (('N', 16, 31, 1), ('Z', 16, 30, 1), ('C', 16, 29, 1...

COND_AL = 14

COND_CC = 3

COND_CS = 2

COND_EQ = 0

COND_EXTENDED = 15

COND_GE = 10

COND_GT = 12

COND_HI = 8

COND_LE = 13

COND_LO = 9

COND_LT = 11

COND_MI = 4

COND_NE = 1

COND_PL = 5

COND_VC = 7

COND_VS = 6

IENC_ARCH_UNDEF = 10

IENC_BRANCH = 13

IENC_COPROC_DP = 16

IENC_COPROC_LOAD = 15

IENC_COPROC_REG_XFER = 17

IENC_COPROC_RREG_XFER = 14

IENC_DP_IMM = 7

IENC_DP_IMM_SHIFT = 0

IENC_DP_REG_SHIFT = 3

IENC_EXTRA_LOAD = 20

IENC_LOAD_IMM_OFF = 8

IENC_LOAD_MULT = 12

IENC_LOAD_REG_OFF = 9

IENC_MEDIA = 11

IENC_MEDIA_EXTEND = 722688

IENC_MEDIA_PARALLEL = 721152

IENC_MEDIA_REV = 721664

IENC_MEDIA_SAT = 721408

IENC_MEDIA_SEL = 721920

IENC_MEDIA_USAD8 = 722176

IENC_MEDIA_USADA8 = 722432

IENC_MISC = 1

IENC_MISC1 = 2

IENC_MOV_IMM_STAT = 6

IENC_MULT = 4

IENC_SWINT = 18

IENC_UNCOND = 19

IENC_UNCOND_BLX = 1246208

IENC_UNCOND_CPS = 1245440

IENC_UNCOND_PLD = 1245952

IENC_UNCOND_SETEND = 1245696

IENC_UNDEF = 5

IF_B = 512

IF_D = 8192

IF_DA = 8388608

IF_DAIB_B = 41943040

IF_DAIB_I = 25165824

IF_DAIB_MASK = 58720256

IF_DAIB_SHFT = 23

IF_DB = 41943040

IF_H = 2048

IF_IA = 25165824

IF_IB = 58720256

IF_L = 16384

IF_PSR_S = 256

IF_S = 4096

IF_T = 32768

IF_UM = 131072

IF_W = 65536

INST_ENC_DP_IMM = 0

INST_ENC_MISC = 1

MODE_ARM = 0

MODE_JAZELLE = 2

MODE_THUMB = 1

OF_UM = 512

OF_W = 256

OSZFMT_BYTE = 'B'

OSZFMT_HWORD = '<H'

OSZFMT_WORD = '<L'

OSZ_BYTE = 1

OSZ_HWORD = 2

OSZ_WORD = 4

PM_abt = 23

PM_fiq = 17

PM_irq = 18

PM_svc = 19

PM_sys = 31

PM_und = 27

PM_usr = 16

PSR_A = 8

PSR_C = 29

PSR_C_bit = 536870912

PSR_C_mask = 3758096383

PSR_E = 9

PSR_F = 6

PSR_GE = 16

PSR_I = 7

PSR_J = 24

PSR_M = 0

PSR_N = 31

PSR_Q = 27

PSR_T = 5

PSR_V = 28

PSR_Z = 30

REG_BP = None
hash(x)

REG_CPSR = 16

REG_FLAGS = 16

REG_FP = 11

REG_IP = 12

REG_LR = 14

REG_OFFSET_ABT = 119

REG_OFFSET_CPSR = 16

REG_OFFSET_FIQ = 17

REG_OFFSET_IRQ = 34

REG_OFFSET_SVC = 51

REG_OFFSET_SYS = 255

REG_OFFSET_UND = 187

REG_OFFSET_USR = 0

REG_PC = 15

REG_R0 = 0

REG_R1 = 1

REG_R2 = 2

REG_R3 = 3

REG_R4 = 4

REG_R5 = 5

REG_R6 = 6

REG_R7 = 7

REG_R8 = 8

REG_R9 = 9

REG_SL = 10

REG_SP = 13

REG_SPSR_abt = 135

REG_SPSR_fiq = 33

REG_SPSR_irq = 50

REG_SPSR_svc = 67

REG_SPSR_sys = 271

REG_SPSR_und = 203

REG_SPSR_usr = 16

SOT_IMM = 1

SOT_REG = 0

S_ASR = 2

S_LSL = 0

S_LSR = 1

S_ROR = 3

S_RRX = 4

__package__ = 'envi.archs.arm'

arm_regs = (('r0', 32), ('r1', 32), ('r2', 32), ('r3', 32), ('...

cond_codes = {0: 'eq', 1: 'ne', 2: 'cs', 3: 'cc', 4: 'mi', 5: ...

daib = ('da', 'ia', 'db', 'ib')

fmts = [None, 1, 2, None, 4]

l = {'ArmMeta': (('N', 16, 31, 1), ('Z', 16, 30, 1), ('C', 16,...

proc_modes = {16: ('User Processor Mode', 'usr', 'Normal progr...

psr_fields = ['M', None, None, None, None, 'T', 'F', 'I', 'A',...

shift_names = ('lsl', 'lsr', 'asr', 'ror', 'rrx')

x = 31

Variables Details

[hide private]

ArmMeta

Value:

(('N', 16, 31, 1),
 ('Z', 16, 30, 1),
 ('C', 16, 29, 1),
 ('V', 16, 28, 1),
 ('Q', 16, 27, 1),
 ('J', 16, 24, 1),
 ('GE', 16, 16, 4),
 ('E', 16, 9, 1),
...

arm_regs

Value:

(('r0', 32),
 ('r1', 32),
 ('r2', 32),
 ('r3', 32),
 ('r4', 32),
 ('r5', 32),
 ('r6', 32),
 ('r7', 32),
...

cond_codes

Value:

{0: 'eq',
 1: 'ne',
 2: 'cs',
 3: 'cc',
 4: 'mi',
 5: 'pl',
 6: 'vs',
 7: 'vc',
...

l

Value:

{'ArmMeta': (('N', 16, 31, 1),
             ('Z', 16, 30, 1),
             ('C', 16, 29, 1),
             ('V', 16, 28, 1),
             ('Q', 16, 27, 1),
             ('J', 16, 24, 1),
             ('GE', 16, 16, 4),
             ('E', 16, 9, 1),
...

proc_modes

Value:

{16: ('User Processor Mode',
      'usr',
      'Normal program execution mode',
      0,
      15,
      16),
 17: ('FIQ Processor Mode',
      'fiq',
...

psr_fields

Value:

['M',
 None,
 None,
 None,
 None,
 'T',
 'F',
 'I',
...