Source Code for Module envi.archs.arm.const

  1  MODE_ARM        = 0 
  2  MODE_THUMB      = 1 
  3  MODE_JAZELLE    = 2 
  4   
  5  #IFLAGS - keep bottom 8-bits for cross-platform flags like envi.IF_NOFALL and envi.IF_BRFALL 
  6  IF_PSR_S     = 1<<8     # This DP instruciton can update CPSR 
  7  IF_B         = 1<<9     # Byte 
  8  IF_H         = 1<<11    # HalfWord 
  9  IF_S         = 1<<12    # Signed 
 10  IF_D         = 1<<13    # Signed 
 11  IF_L         = 1<<14    # Long-store (eg. Dblword Precision) for STC 
 12  IF_T         = 1<<15    # Translate for strCCbt 
 13  IF_W         = 1<<16    # Write Back for STM/LDM (!) 
 14  IF_UM        = 1<<17    # User Mode Registers for STM/LDM (^) (obviously no R15) 
 15  IF_DAIB_MASK = 0x3800000 
 16  IF_DAIB_SHFT = 23 
 17  IF_DA        = 0x0800000  # Decrement After 
 18  IF_IA        = 0x1800000  # Increment After 
 19  IF_DB        = 0x2800000  # Decrement Before 
 20  IF_IB        = 0x3800000  # Increment Before 
 21  IF_DAIB_B    = 0x2800000  # Before mask  
 22  IF_DAIB_I    = 0x1800000  # Before mask  
 23   
 24   
 25  OF_W         = 1<<8     # Write back to  
 26  OF_UM        = 1<<9     # Usermode, or if r15 included set current SPSR -> CPSR 
 27   
 28   
 29  OSZFMT_BYTE = "B" 
 30  OSZFMT_HWORD = "<H"  # Introduced in ARMv4 
 31  OSZFMT_WORD = "<L" 
 32  OSZ_BYTE = 1 
 33  OSZ_HWORD = 2 
 34  OSZ_WORD = 4 
 35   
 36  fmts = [None, OSZ_BYTE, OSZ_HWORD, None, OSZ_WORD] 
 37   
 38  COND_EQ     = 0x0        # z==1  (equal) 
 39  COND_NE     = 0x1        # z==0  (not equal) 
 40  COND_CS     = 0x2        # c==1  (carry set/unsigned higher or same) 
 41  COND_CC     = 0x3        # c==0  (carry clear/unsigned lower) 
 42  COND_MI     = 0x4        # n==1  (minus/negative) 
 43  COND_PL     = 0x5        # n==0  (plus/positive or zero) 
 44  COND_VS     = 0x6        # v==1  (overflow) 
 45  COND_VC     = 0x7        # v==0  (no overflow) 
 46  COND_HI     = 0x8        # c==1 and z==0  (unsigned higher) 
 47  COND_LO     = 0x9        # c==0  or z==1  (unsigned lower or same) 
 48  COND_GE     = 0xA        # n==v  (signed greater than or equal)  (n==1 and v==1) or (n==0 and v==0) 
 49  COND_LT     = 0xB        # n!=v  (signed less than)  (n==1 and v==0) or (n==0 and v==1) 
 50  COND_GT     = 0xC        # z==0 and n==v (signed greater than) 
 51  COND_LE     = 0xD        # z==1 and n!=v (signed less than or equal) 
 52  COND_AL     = 0xE        # always 
 53  COND_EXTENDED = 0xF        # special case - see conditional 0b1111 
 54   
 55  cond_codes = { 
 56  COND_EQ:"eq", # Equal Z set  
 57  COND_NE:"ne", # Not equal Z clear  
 58  COND_CS:"cs", #/HS Carry set/unsigned higher or same C set  
 59  COND_CC:"cc", #/LO Carry clear/unsigned lower C clear  
 60  COND_MI:"mi", # Minus/negative N set  
 61  COND_PL:"pl", # Plus/positive or zero N clear  
 62  COND_VS:"vs", # Overflow V set  
 63  COND_VC:"vc", # No overflow V clear  
 64  COND_HI:"hi", # Unsigned higher C set and Z clear  
 65  COND_LO:"lo", # Unsigned lower or same C clear or Z set  
 66  COND_GE:"ge", # Signed greater than or equal N set and V set, or N clear and V clear (N == V)  
 67  COND_LT:"lt", # Signed less than N set and V clear, or N clear and V set (N!= V)  
 68  COND_GT:"gt", # Signed greater than Z clear, and either N set and V set, or N clear and V clear (Z == 0,N == V)  
 69  COND_LE:"le", # Signed less than or equal Z set, or N set and V clear, or N clear and V set (Z == 1 or N!= V)  
 70  COND_AL:"", # Always (unconditional) - could be "al" but "" seems better... 
 71  COND_EXTENDED:"2", # See extended opcode table 
 72  } 
 73   
 74  PM_usr = 0b10000 
 75  PM_fiq = 0b10001 
 76  PM_irq = 0b10010 
 77  PM_svc = 0b10011 
 78  PM_abt = 0b10111 
 79  PM_und = 0b11011 
 80  PM_sys = 0b11111 
 81   
 82  # reg stuff stolen from regs.py to support proc_modes 
 83  REG_OFFSET_USR = 17 * (PM_usr&0xf) 
 84  REG_OFFSET_FIQ = 17 * (PM_fiq&0xf) 
 85  REG_OFFSET_IRQ = 17 * (PM_irq&0xf) 
 86  REG_OFFSET_SVC = 17 * (PM_svc&0xf) 
 87  REG_OFFSET_ABT = 17 * (PM_abt&0xf) 
 88  REG_OFFSET_UND = 17 * (PM_und&0xf) 
 89  REG_OFFSET_SYS = 17 * (PM_sys&0xf) 
 90  #REG_OFFSET_CPSR = 17 * 16 
 91  REG_OFFSET_CPSR = 16                    # CPSR is available in every mode, and PM_usr and PM_sys don't have an SPSR. 
 92   
 93  REG_SPSR_usr = REG_OFFSET_USR + 16 
 94  REG_SPSR_fiq = REG_OFFSET_FIQ + 16 
 95  REG_SPSR_irq = REG_OFFSET_IRQ + 16 
 96  REG_SPSR_svc = REG_OFFSET_SVC + 16 
 97  REG_SPSR_abt = REG_OFFSET_ABT + 16 
 98  REG_SPSR_und = REG_OFFSET_UND + 16 
 99  REG_SPSR_sys = REG_OFFSET_SYS + 16 
100   
101  REG_PC = 0xf 
102  REG_SP = 0xd 
103  REG_BP = None 
104  REG_CPSR = REG_OFFSET_CPSR 
105  REG_FLAGS = REG_OFFSET_CPSR    #same location, backward-compat name 
106   
107  proc_modes = { # mode_name, short_name, description, offset, mode_reg_count, PSR_offset 
108      PM_usr: ("User Processor Mode", "usr", "Normal program execution mode", REG_OFFSET_USR, 15, REG_SPSR_usr), 
109      PM_fiq: ("FIQ Processor Mode", "fiq", "Supports a high-speed data transfer or channel process", REG_OFFSET_FIQ, 8, REG_SPSR_fiq), 
110      PM_irq: ("IRQ Processor Mode", "irq", "Used for general-purpose interrupt handling", REG_OFFSET_IRQ, 13, REG_SPSR_irq), 
111      PM_svc: ("Supervisor Processor Mode", "svc", "A protected mode for the operating system", REG_OFFSET_SVC, 13, REG_SPSR_svc), 
112      PM_abt: ("Abort Processor Mode", "abt", "Implements virtual memory and/or memory protection", REG_OFFSET_ABT, 13, REG_SPSR_abt), 
113      PM_und: ("Undefined Processor Mode", "und", "Supports software emulation of hardware coprocessor", REG_OFFSET_UND, 13, REG_SPSR_und), 
114      PM_sys: ("System Processor Mode", "sys", "Runs privileged operating system tasks (ARMv4 and above)", REG_OFFSET_SYS, 15, REG_SPSR_sys), 
115  } 
116   
117  INST_ENC_DP_IMM = 0 # Data Processing Immediate Shift 
118  INST_ENC_MISC   = 1 # Misc Instructions 
119   
120  # Instruction encodings in arm v5 
121  IENC_DP_IMM_SHIFT = 0 # Data processing immediate shift 
122  IENC_MISC         = 1 # Miscellaneous instructions 
123  IENC_MISC1        = 2 # Miscellaneous instructions again 
124  IENC_DP_REG_SHIFT = 3 # Data processing register shift 
125  IENC_MULT         = 4 # Multiplies & Extra load/stores 
126  IENC_UNDEF        = 5 # Undefined instruction 
127  IENC_MOV_IMM_STAT = 6 # Move immediate to status register 
128  IENC_DP_IMM       = 7 # Data processing immediate 
129  IENC_LOAD_IMM_OFF = 8 # Load/Store immediate offset 
130  IENC_LOAD_REG_OFF = 9 # Load/Store register offset 
131  IENC_ARCH_UNDEF   = 10 # Architecturally undefined 
132  IENC_MEDIA        = 11 # Media instructions 
133  IENC_LOAD_MULT    = 12 # Load/Store Multiple 
134  IENC_BRANCH       = 13 # Branch 
135  IENC_COPROC_RREG_XFER = 14  # mrrc/mcrr 
136  IENC_COPROC_LOAD  = 15 # Coprocessor load/store and double reg xfers 
137  IENC_COPROC_DP    = 16 # Coprocessor data processing 
138  IENC_COPROC_REG_XFER = 17 # Coprocessor register transfers 
139  IENC_SWINT        = 18 # Sofware interrupts 
140  IENC_UNCOND       = 19 # unconditional wacko instructions 
141  IENC_EXTRA_LOAD   = 20 # extra load/store (swp) 
142   
143  # offchutes 
144  IENC_MEDIA_PARALLEL = ((IENC_MEDIA << 8) + 1) << 8 
145  IENC_MEDIA_SAT      = ((IENC_MEDIA << 8) + 2) << 8 
146  IENC_MEDIA_REV      = ((IENC_MEDIA << 8) + 3) << 8 
147  IENC_MEDIA_SEL      = ((IENC_MEDIA << 8) + 4) << 8 
148  IENC_MEDIA_USAD8    = ((IENC_MEDIA << 8) + 5) << 8 
149  IENC_MEDIA_USADA8   = ((IENC_MEDIA << 8) + 6) << 8 
150  IENC_MEDIA_EXTEND   = ((IENC_MEDIA << 8) + 7) << 8 
151  IENC_UNCOND_CPS     = ((IENC_UNCOND << 8) + 1) << 8 
152  IENC_UNCOND_SETEND  = ((IENC_UNCOND << 8) + 2) << 8 
153  IENC_UNCOND_PLD     = ((IENC_UNCOND << 8) + 3) << 8 
154  IENC_UNCOND_BLX     = ((IENC_UNCOND << 8) + 4) << 8 
155   
156   
157  # The supported types of operand shifts (by the 2 bit field) 
158  S_LSL = 0 
159  S_LSR = 1 
160  S_ASR = 2 
161  S_ROR = 3 
162  S_RRX = 4 # FIXME HACK XXX add this 
163   
164  shift_names = ("lsl", "lsr", "asr", "ror", "rrx") 
165   
166  SOT_REG = 0 
167  SOT_IMM = 1 
168   
169  daib = ("da","ia","db","ib") 
170