Source Code for Module envi.archs.amd64.regs

  1  import envi.registers as e_reg 
  2  import envi.archs.i386 as e_i386 
  3  
 
  4  # NOTE: all REX_R registers must *directly* follow their 3 bit variants
 
  5  #       in the table below
 
  6  amd64regs = [
 
  7      ("rax",64),("rcx",64),("rdx",64),("rbx",64),("rsp",64),("rbp",64),("rsi",64),("rdi",64),
 
  8      # The amd64 extended GP regs
 
  9      ("r8",64),("r9",64),("r10",64),("r11",64),("r12",64),("r13",64),("r14",64),("r15",64),
 
 10  
 
 11      ("mm0",64),("mm1",64), ("mm2",64), ("mm3",64), ("mm4",64), ("mm5",64), ("mm6",64), ("mm7",64),
 
 12  
 
 13      # SIMD registers
 
 14      ("xmm0",128),("xmm1",128),("xmm2",128),("xmm3",128),("xmm4",128),("xmm5",128),("xmm6",128),("xmm7",128),
 
 15      # The amd64 extended SIMD regs...
 
 16      ("xmm8",128),("xmm9",128),("xmm10",128),("xmm11",128),("xmm12",128),("xmm13",128),("xmm14",128),("xmm15",128),
 
 17  
 
 18      # Debug registers
 
 19      ("debug0",64),("debug1",64),("debug2",64),("debug3",64),("debug4",64),("debug5",64),("debug6",64),("debug7",64),
 
 20      # Extended Debug registers (REX.R)
 
 21      ("debug8",64),("debug9",64),("debug10",64),("debug11",64),("debug12",64),("debug13",64),("debug14",64),("debug15",64),
 
 22  
 
 23      # Control registers
 
 24      ("ctrl0",64),("ctrl1",64),("ctrl2",64),("ctrl3",64),("ctrl4",64),("ctrl5",64),("ctrl6",64),("ctrl7",64),
 
 25      # Extended Control registers (REX.R)
 
 26      ("ctrl8",64),("ctrl9",64),("ctrl10",64),("ctrl11",64),("ctrl12",64),("ctrl13",64),("ctrl14",64),("ctrl15",64),
 
 27  
 
 28      # Test registers
 
 29      ("test0", 32),("test1", 32),("test2", 32),("test3", 32),("test4", 32),("test5", 32),("test6", 32),("test7", 32),
 
 30      # Segment registers
 
 31      ("es", 16),("cs",16),("ss",16),("ds",16),("fs",16),("gs",16),
 
 32      # FPU Registers
 
 33      ("st0", 128),("st1", 128),("st2", 128),("st3", 128),("st4", 128),("st5", 128),("st6", 128),("st7", 128),
 
 34      # Leftovers ;)
 
 35      ("eflags", 32), ("rip", 64),
 
 36  ] 
 37  
 
 38  # Build up a set of accessable constants
 
 39  l = locals() 
 40  e_reg.addLocalEnums(l, amd64regs) 
 41  
 
 42  amd64meta = e_i386.i386meta + [
 
 43      ("eax", REG_RAX, 0, 32),
 
 44      ("ecx", REG_RCX, 0, 32),
 
 45      ("edx", REG_RDX, 0, 32),
 
 46      ("ebx", REG_RBX, 0, 32),
 
 47      ("esp", REG_RSP, 0, 32),
 
 48      ("ebp", REG_RBP, 0, 32),
 
 49      ("esi", REG_RSI, 0, 32),
 
 50      ("edi", REG_RDI, 0, 32),
 
 51  
 
 52      ("ax", REG_RAX, 0, 16),
 
 53      ("cx", REG_RCX, 0, 16),
 
 54      ("dx", REG_RDX, 0, 16),
 
 55      ("bx", REG_RBX, 0, 16),
 
 56      ("sp", REG_RSP, 0, 16),
 
 57      ("bp", REG_RBP, 0, 16),
 
 58      ("si", REG_RSI, 0, 16),
 
 59      ("di", REG_RDI, 0, 16),
 
 60  
 
 61      ("al", REG_RAX, 0, 8),
 
 62      ("cl", REG_RCX, 0, 8),
 
 63      ("dl", REG_RDX, 0, 8),
 
 64      ("bl", REG_RBX, 0, 8),
 
 65  
 
 66      ("ah", REG_RAX, 8, 8),
 
 67      ("ch", REG_RCX, 8, 8),
 
 68      ("dh", REG_RDX, 8, 8),
 
 69      ("bh", REG_RBX, 8, 8),
 
 70  
 
 71      # NOTE: with a REX prefix, all ah/ch regs get
 
 72      # mapped back to being sil/dil etc...
 
 73      ("spl", REG_RSP, 8, 8),
 
 74      ("bpl", REG_RBP, 8, 8),
 
 75      ("sil", REG_RSI, 8, 8),
 
 76      ("dil", REG_RDI, 8, 8),
 
 77  
 
 78      # The new GP regs are accessible in all modes.
 
 79      ("r8d",  REG_R8,  0, 32),
 
 80      ("r9d",  REG_R9,  0, 32),
 
 81      ("r10d", REG_R10, 0, 32),
 
 82      ("r11d", REG_R11, 0, 32),
 
 83      ("r12d", REG_R12, 0, 32),
 
 84      ("r13d", REG_R13, 0, 32),
 
 85      ("r14d", REG_R14, 0, 32),
 
 86      ("r15d", REG_R15, 0, 32),
 
 87  
 
 88      ("r8w",  REG_R8,  0, 16),
 
 89      ("r9w",  REG_R9,  0, 16),
 
 90      ("r10w", REG_R10, 0, 16),
 
 91      ("r11w", REG_R11, 0, 16),
 
 92      ("r12w", REG_R12, 0, 16),
 
 93      ("r13w", REG_R13, 0, 16),
 
 94      ("r14w", REG_R14, 0, 16),
 
 95      ("r15w", REG_R15, 0, 16),
 
 96  
 
 97      ("r8l",  REG_R8,  0, 8),
 
 98      ("r9l",  REG_R9,  0, 8),
 
 99      ("r10l", REG_R10, 0, 8),
 
100      ("r11l", REG_R11, 0, 8),
 
101      ("r12l", REG_R12, 0, 8),
 
102      ("r13l", REG_R13, 0, 8),
 
103      ("r14l", REG_R14, 0, 8),
 
104      ("r15l", REG_R15, 0, 8),
 
105  
 
106      # Flags
 
107      ("TF", REG_EFLAGS, 8, 1),
 
108  ] 
109  
 
110  # Add the meta's indexes
 
111  e_reg.addLocalMetas(l, amd64meta) 
112  
 
113  RMETA_LOW32 = 0x00200000 
114  
 
115 -class Amd64RegisterContext(e_reg.RegisterContext): 
116 -    def __init__(self): 
117          self.loadRegDef(amd64regs) 
118          self.loadRegMetas(amd64meta) 
119          self.setRegisterIndexes(REG_RIP, REG_RSP) 
120  
 
121 -    def setRegister(self, index, value): 
122          # NOTE: A special override is needed here because setting "eax" automagicall
 
123          # zero extends into RAX...
 
124          if (index & 0xffff0000) == RMETA_LOW32: 
125              index = index & 0xffff 
126          e_reg.RegisterContext.setRegister(self, index, value) 
127