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1 """ 2 The envi architecuture module for the AMD 64 platform. 3 """ 4 import envi 5 import envi.bits as e_bits 6 import envi.registers as e_reg 7 import envi.archs.i386 as e_i386 8 9 from envi.archs.amd64.regs import * 10 from envi.archs.amd64.disasm import * 11 12 # NOTE: The REX prefixes don't end up with displayed names 13 # NOTE: the REX prefix must be the *last* non escape (0f) prefix 14 15 # EMU NOTES: 16 # In 64 bit mode, all 32 bit dest regs get 0 extended into the rest of the bits 17 # In 64 bit mode, all 8/16 bit accesses do NOT modify the upper bits 18 # In 64 bit mode, all near branches, and implicit RSP (push pop) use RIP even w/o REX 19 # In 64 bit mode, if mod/rm is mod=0 and r/m is 5, it's RIP relative IMM32 20 384062 63 amd64call = Amd64Call() 6442 ret = [] 43 if count == 0: return ret 44 ret.append(emu.getRegister(REG_RCX)) 45 if count == 1: return ret 46 ret.append(emu.getRegister(REG_RDX)) 47 if count == 2: return ret 48 ret.append(emu.getRegister(REG_R8)) 49 if count == 3: return ret 50 ret.append(emu.getRegister(REG_R9)) 51 if count == 4: return ret 52 rsp = emu.getStackCounter() 53 stargs = emu.readMemoryFormat(rsp, "<12Q") 54 ret.extend(stargs[4:]) 55 return ret[:count]5658 rsp = emu.getStackCounter() 59 rsp += 8 60 emu.setStackCounter(rsp) 61 emu.setRegister(REG_RAX, value)7367 e_i386.IntelEmulator.__init__(self) 68 # The above sets up the intel reg context, so we smash over it 69 Amd64RegisterContext.__init__(self) 70 # For the format calls in reading memory 71 self.imem_psize = 8 72 self.addCallingConvention("amd64call", amd64call)
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