Bases: envi.ArchitectureModule
The guts for the i386 envi opcode disassembler.
Bases: envi.DerefOper
An operand which represents the dereference (memory read/write) of a memory location associated with an immediate.
Bases: envi.ImmedOper
An operand representing an immediate.
Bases: envi.Opcode
Bases: envi.Operand
This is the operand used for EIP relative offsets for operands on instructions like jmp/call
Bases: envi.DerefOper
An operand which represents the result of reading/writting memory from the dereference (with possible displacement) from a given register.
Bases: envi.RegisterOper
Bases: envi.DerefOper
An operand which represents the result of reading/writting memory from the dereference (with possible displacement) from a given register.
Home for the i386 emulation code.
Bases: envi.archs.i386.emu.FastCall
Bases: envi.CallingConvention
Bases: envi.CallingConvention
Bases: envi.archs.i386.regs.i386RegisterContext, envi.Emulator
Compare the dword pointed at by ds:esi to ds:edi. (if equal, update esi/edi by one acording to DF)
Do the core of integer subtraction but only return the resulting value rather than assigning it. (allows cmp and sub to use the same code)
Bases: envi.archs.i386.emu.FastCall
Bases: envi.archs.i386.emu.StdCall
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
(optable, optype, operand 0, operand 1, operand 2, CPU required, “opcodename”, op0Register, op1Register, op2Register)
### These values allow an opcode to be sliced and diced to make it fit correctly into the current lookup table. # # (tbl32_0F, 0, 0xff, 0, 0xff), # (tbl32_80, 3, 0x07, 0, 0xff, 4), # # Table pointer # shift bits right (eg. >> 4 makes each line in the table valid for 16 numbers... ie 0xc0-0xcf are all one entry in the table) # mask part of the byte (eg. & 0x7 only makes use of the 00000111 bits...) # simple subtraction # highest acceptable value # tables86 entry to handle the falloff (from the previous check)