arm Package

arm Package

The initial arm module.

class envi.archs.arm.ArmModule

Bases: envi.ArchitectureModule

archGetBreakInstr()

archGetRegCtx()

getEmulator()

getPointerSize()

makeOpcode(bytes, offset=0, va=0)

Parse a sequence of bytes out into an envi.Opcode instance.

pointerString(va)

setModeThumb()

armdisasm Module

class envi.archs.arm.armdisasm.ArmCoprocOpcodeOper(val)

Bases: envi.Operand

getOperValue(op, emu=None)

involvesPC()

repr(op)

class envi.archs.arm.armdisasm.ArmCoprocOper(val)

Bases: envi.Operand

getOperValue(op, emu=None)

involvesPC()

repr(op)

class envi.archs.arm.armdisasm.ArmCoprocRegOper(val, shtype=None, shval=None)

Bases: envi.Operand

getOperValue(op, emu=None)

involvesPC()

repr(op)

class envi.archs.arm.armdisasm.ArmEndianOper(val, shval=0, shtype=3)

Bases: envi.archs.arm.armdisasm.ArmImmOper

getOperValue(op, emu=None)

involvesPC()

repr(op)

class envi.archs.arm.armdisasm.ArmImmOffsetOper(base_reg, offset, va, pubwl=8)

Bases: envi.Operand

getOperValue(op, emu=None)

involvesPC()

render(mcanv, op, idx)

repr(op)

class envi.archs.arm.armdisasm.ArmImmOper(val, shval=0, shtype=3)

Bases: envi.Operand

getOperValue(op, emu=None)

involvesPC()

render(mcanv, op, idx)

repr(op)

class envi.archs.arm.armdisasm.ArmOffsetOper(val, va)

Bases: envi.Operand

getOperValue(op, emu=None)

involvesPC()

render(mcanv, op, idx)

repr(op)

class envi.archs.arm.armdisasm.ArmOpcode(va, opcode, mnem, prefixes, size, operands, iflags=0)

Bases: envi.Opcode

getBranches(emu=None)

Return a list of tuples. Each tuple contains the target VA of the branch, and a possible set of flags showing what type of branch it is.

See the BR_FOO types for all the supported envi branch flags.... Example: for bva,bflags in op.getBranches():

render(mcanv)

Render this opcode to the specified memory canvas

class envi.archs.arm.armdisasm.ArmPSRFlagsOper(flags)

Bases: envi.Operand

getOperValue(op, emu=None)

involvesPC()

repr(op)

class envi.archs.arm.armdisasm.ArmPgmStatFlagsOper(val)

Bases: envi.Operand

getOperValue(op, emu=None)

involvesPC()

repr(op)

class envi.archs.arm.armdisasm.ArmPgmStatRegOper(val)

Bases: envi.Operand

getOperValue(op, emu=None)

involvesPC()

repr(op)

class envi.archs.arm.armdisasm.ArmRegListOper(val, oflags=0)

Bases: envi.Operand

getOperValue(op, emu=None)

involvesPC()

render(mcanv, op, idx)

repr(op)

class envi.archs.arm.armdisasm.ArmRegOffsetOper(base_reg, offset_reg, va, pubwl=0)

Bases: envi.Operand

getOperValue(op, emu=None)

involvesPC()

render(mcanv, op, idx)

repr(op)

class envi.archs.arm.armdisasm.ArmRegOper(reg, oflags=0)

Bases: envi.Operand

getOperValue(op, emu=None)

involvesPC()

render(mcanv, op, idx)

repr(op)

setOperValue(op, emu=None, val=None)

class envi.archs.arm.armdisasm.ArmRegShiftImmOper(reg, shtype, shimm)

Bases: envi.Operand

getOperValue(op, emu=None)

involvesPC()

render(mcanv, op, idx)

repr(op)

class envi.archs.arm.armdisasm.ArmRegShiftRegOper(reg, shtype, shreg)

Bases: envi.Operand

getOperValue(op, emu=None)

involvesPC()

render(mcanv, op, idx)

repr(op)

class envi.archs.arm.armdisasm.ArmScaledOffsetOper(base_reg, offset_reg, shtype, shval, va, pubwl=0)

Bases: envi.Operand

getOperValue(op, emu=None)

involvesPC()

render(mcanv, op, idx)

repr(op)

class envi.archs.arm.armdisasm.ArmStdDisasm

checkSetMode(op)

disasm(bytes, offset, va, trackMode=False)

Parse a sequence of bytes out into an envi.Opcode instance.

envi.archs.arm.armdisasm.addrToName(mcanv, va)

envi.archs.arm.armdisasm.chopmul(opcode)

envi.archs.arm.armdisasm.dpbase(opval)

Parse and return opcode,sflag,Rn,Rd for a standard dataprocessing instruction.

envi.archs.arm.armdisasm.instrenc(encoding, index)

envi.archs.arm.armdisasm.p_arch_undef(opval, va)

envi.archs.arm.armdisasm.p_branch(opval, va)

envi.archs.arm.armdisasm.p_coproc_dbl_reg_xfer(opval, va)

envi.archs.arm.armdisasm.p_coproc_dp(opval, va)

envi.archs.arm.armdisasm.p_coproc_load(opval, va)

envi.archs.arm.armdisasm.p_coproc_reg_xfer(opval, va)

envi.archs.arm.armdisasm.p_dp_imm(opval, va)

envi.archs.arm.armdisasm.p_dp_imm_shift(opval, va)

envi.archs.arm.armdisasm.p_dp_reg_shift(opval, va)

envi.archs.arm.armdisasm.p_extra_load_store(opval, va)

envi.archs.arm.armdisasm.p_load_imm_off(opval, va)

envi.archs.arm.armdisasm.p_load_mult(opval, va)

envi.archs.arm.armdisasm.p_load_reg_off(opval, va)

envi.archs.arm.armdisasm.p_media(opval, va)

27:20, 7:4

envi.archs.arm.armdisasm.p_media_pack_sat_rev_extend(opval, va)

envi.archs.arm.armdisasm.p_media_parallel(opval, va)

envi.archs.arm.armdisasm.p_media_smul(opval, va)

envi.archs.arm.armdisasm.p_media_usada(opval, va)

envi.archs.arm.armdisasm.p_misc(opval, va)

envi.archs.arm.armdisasm.p_misc1(opval, va)

envi.archs.arm.armdisasm.p_mov_imm_stat(opval, va)

envi.archs.arm.armdisasm.p_mult(opval, va)

envi.archs.arm.armdisasm.p_swint(opval, va)

envi.archs.arm.armdisasm.p_uncond(opval, va)

envi.archs.arm.armdisasm.p_undef(opval, va)

envi.archs.arm.armdisasm.sh_asr(num, shval)

envi.archs.arm.armdisasm.sh_lsl(num, shval)

envi.archs.arm.armdisasm.sh_lsr(num, shval)

envi.archs.arm.armdisasm.sh_ror(num, shval)

envi.archs.arm.armdisasm.sh_rrx(num, shval, emu=None)

const Module

disasm Module

class envi.archs.arm.disasm.ArmDisasm

disasm(bytes, offset, va, trackMode=True, mode=None)

setMode(mode_num)

class envi.archs.arm.disasm.ArmJazDisasm

disasm(bytes, offset, va, trackMode=True)

emu Module

The initial arm module.

class envi.archs.arm.emu.ArmArchitectureProcedureCall

Bases: envi.CallingConvention

Implement calling conventions for your arch.

getCallArgs(emu, count)

setReturnValue(emu, value, ccinfo=None)

class envi.archs.arm.emu.ArmEmulator

Bases: envi.archs.arm.ArmModule, envi.archs.arm.regs.ArmRegisterContext, envi.Emulator

doPop()

doPush(val)

executeOpcode(op)

getCPSR()

getFlag(which, mode=16)

getProcMode()

getRegister(index, mode=None)

Return the current value of the specified register index.

getSPSR(mode)

i_add(op)

i_and(op)

i_b(op)

i_bl(op)

i_cdp(op)

i_eor(op)

i_ldc(op)

i_ldm(op)

i_ldmia(op)

i_ldr(op)

i_mcr(op)

i_mcrr(op)

i_mrc(op)

i_mrrc(op)

i_rsb(op)

i_stc(op)

i_stm(op)

i_stmia(op)

i_sub(op)

i_tst(op)

intSubBase(src1, src2, Sflag=0, rd=0)

integerSubtraction(op)

Do the core of integer subtraction but only return the resulting value rather than assigning it. (allows cmp and sub to use the same code)

logicalAnd(op)

readMemSignedValue(addr, size)

readMemValue(addr, size)

setCPSR(psr)

setFlag(which, state, mode=16)

setProcMode(mode)

setRegister(index, value, mode=None)

Set a register value by index.

setSPSR(mode, psr)

undefFlags()

Used in PDE. A flag setting operation has resulted in un-defined value. Set the flags to un-defined as well.

writeMemValue(addr, value, size)

class envi.archs.arm.emu.CoProcEmulator

cdp(parms)

ldc(parms)

mcr(parms)

mcrr(parms)

mrc(parms)

mrrc(parms)

stc(parms)

regs Module

class envi.archs.arm.regs.ArmRegisterContext

Bases: envi.registers.RegisterContext

thumb Module

thumbdisasm Module

class envi.archs.arm.thumbdisasm.ArmThumbDisasm

disasm(bytes, offset, va, trackMode=True)

class envi.archs.arm.thumbdisasm.ThumbOpcode(va, opcode, mnem, prefixes, size, operands, iflags=0)

Bases: envi.archs.arm.armdisasm.ArmOpcode

envi.archs.arm.thumbdisasm.d1_rm4_rd3(va, value)

envi.archs.arm.thumbdisasm.imm5_rn_rt(va, value)

envi.archs.arm.thumbdisasm.is_thumb32(val)

Take a 16 bit integer (opcode) value and determine if it is really the first 16 bits of a 32 bit instruction.

envi.archs.arm.thumbdisasm.ldmia(va, value)

envi.archs.arm.thumbdisasm.rd_pc_imm8(va, value)

envi.archs.arm.thumbdisasm.rd_sp_imm8(va, value)

envi.archs.arm.thumbdisasm.rm_reglist(va, value)

envi.archs.arm.thumbdisasm.rm_rn_rt(va, value)

envi.archs.arm.thumbdisasm.rt_pc_imm8(va, value)

envi.archs.arm.thumbdisasm.shmaskval(value, shval, mask)

class envi.archs.arm.thumbdisasm.simpleops(*operdef)

envi.archs.arm.thumbdisasm.sp_sp_imm7(va, value)